Datasheet

© 2009-2012 Microchip Technology Inc. Preliminary DS70616F-page 173
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
REGISTER 8-13: DMALCA: DMA LAST CHANNEL ACTIVE DMA STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-1 R-1 R-1 R-1
— — — — LSTCH<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0’
bit 3-0 LSTCH<3:0>: Last DMAC Channel Active Status bits
1111 = No DMA transfer has occurred since system Reset
1110 = Last data transfer was handled by Channel 14
1101 = Last data transfer was handled by Channel 13
1100 = Last data transfer was handled by Channel 12
1011 = Last data transfer was handled by Channel 11
1010 = Last data transfer was handled by Channel 10
1001 = Last data transfer was handled by Channel 9
1000 = Last data transfer was handled by Channel 8
0111 = Last data transfer was handled by Channel 7
0110 = Last data transfer was handled by Channel 6
0101 = Last data transfer was handled by Channel 5
0100 = Last data transfer was handled by Channel 4
0011 = Last data transfer was handled by Channel 3
0010 = Last data transfer was handled by Channel 2
0001 = Last data transfer was handled by Channel 1
0000 = Last data transfer was handled by Channel 0