Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 172 Preliminary © 2009-2012 Microchip Technology Inc.
bit 2 RQCOL2: Channel 2 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
bit 1 RQCOL1: Channel 1 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
bit 0 RQCOL0: Channel 0 Transfer Request Collision Flag bit
1 = User FORCE and Interrupt-based request collision detected
0 = No request collision detected
REGISTER 8-12: DMARQC: DMA REQUEST COLLISION STATUS REGISTER (CONTINUED)