Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 162 Preliminary © 2009-2012 Microchip Technology Inc.
8.1 DMA Resources
Many useful resources related to DMA are provided on
the main product page of the Microchip web site for the
devices listed in this data sheet. This product page,
which can be accessed using this link, contains the
latest updates and additional information.
8.1.1 KEY RESOURCES
• Section 22. “Direct Memory Access (DMA)”
(DS70348)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33E/PIC24E Family Reference
Manuals Sections
• Development Tools
8.2 DMAC Registers
Each DMAC Channel x (where x = 0 through 14)
contains the following registers:
• 16-bit DMA Channel Control register (DMAxCON)
• 16-bit DMA Channel IRQ Select register
(DMAxREQ)
• 32-bit DMA RAM Primary Start Address register
(DMAxSTA)
• 32-bit DMA RAM Secondary Start Address
register (DMAxSTB)
• 16-bit DMA Peripheral Address register (DMAxPAD)
• 14-bit DMA Transfer Count register (DMAxCNT)
Additional status registers (DMAPWC, DMARQC,
DMAPPS, DMALCA, and DSADR) are common to all
DMAC channels. These status registers provide infor-
mation on write and request collisions, as well as on
last address and channel access information.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
an IECx register in the interrupt controller, and the
corresponding interrupt priority control bits (DMAxIP)
are located in an IPCx register in the interrupt
controller.
Note: In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en554310