Datasheet

© 2009-2012 Microchip Technology Inc. Preliminary DS70616F-page 161
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
FIGURE 8-2: DMA CONTROLLER BLOCK DIAGRAM
UART4TX – UART4 Transmitter 01011001 — 0x02B4 (U4TXREG)
ECAN1 – RX Data Ready 00100010 0x0440 (C1RXD) —
ECAN1 – TX Data Request 01000110 — 0x0442 (C1TXD)
ECAN2 – RX Data Ready 00110111 0x0540 (C2RXD) —
ECAN2 – TX Data Request 01000111 — 0x0542 (C2TXD)
DCI – DCI Transfer Done 00111100 0x0290 (RXBUF0) 0x0298 (TXBUF0)
ADC1 – ADC1 Convert Done 00001101 0x0300 (ADC1BUF0) —
ADC2 – ADC2 Convert Done 00010101 0x0340 (ADC2BUF0) —
PMP – PMP Data Move 00101101 0x0608 (PMDIN1) 0x0608 (PMDIN1)
TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS (CONTINUED)
Peripheral to DMA Association
DMAxREQ Register
IRQSEL<7:0> Bits
DMAxPAD Register
(Values to Read from
Peripheral)
DMAxPAD Register
(Values to Write to
Peripheral)
CPU
Arbiter
DPSRAM
Peripheral 1
DMA
Peripheral
Non-DMA
PORT 2PORT 1
Peripheral 2
DMA
Ready
Peripheral 3
DMA
Ready
Ready
DMA X-Bus
CPU DMA
CPU DMA
CPU DMA
Peripheral Indirect Address
Note: CPU and DMA address buses are not shown for clarity.
DMA
Control
DMA Controller
DMA
Channels
CPU Peripheral X-Bus
IRQ to DMA
and Interrupt
Controller
Modules
SRAM X-Bus
IRQ to DMA and
Interrupt Controller
Modules
IRQ to DMA and
Interrupt Controller
Modules
01 2 3 N
SRAM
4
··