Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814

FIGURE 7-1: dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814

INTERRUPT VECTOR TABLE

IVT

Decreasing Natural Order Priority

Reset – GOTO Instruction

(1)

0x000000

Reset – GOTO Address

(1)

0x000002

Oscillator Fail Trap Vector 0x000004

Address Error Trap Vector 0x000006

Generic Hard Trap Vector 0x000008

Stack Error Trap Vector 0x00000A

Math Error Trap Vector 0x00000C

DMAC Error Trap Vector 0x00000E

Generic Soft Trap Vector 0x000010

Reserved 0x000012

Interrupt Vector 0 0x000014

Interrupt Vector 1 0x000016

Interrupt Vector 52 0x00007C

Interrupt Vector 53 0x00007E

Interrupt Vector 54 0x000080

Interrupt Vector 116 0x0000FC

Interrupt Vector 117 0x0000FE

Interrupt Vector 118 0x000100

Interrupt Vector 119 0x000102

Interrupt Vector 120 0x000104

Interrupt Vector 244 0x0001FC

Interrupt Vector 245 0x0001FE

START OF CODE 0x000200

See Tabl e 7- 1 for

Interrupt Vector details

Note 1: Reset locations are also located in the Auxiliary Segment at the addresses 0x7FFFFC and

0x7FFFFE. The Reset Target Vector Select bit, RSTPRI (FICD<2>) controls whether the

primary (General Segment) or Auxiliary Segment reset location is used.