Datasheet
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616F-page 136 Preliminary © 2009-2012 Microchip Technology Inc.
5.2 RTSP Operation
The dsPIC33EPXXX(GP/MC/MU)806/810/814 and
PIC24EPXXX(GP/GU)810/814 Flash program memory
array is organized into rows of 128 instructions or 384
bytes. RTSP allows the user application to erase a
page of memory, which consists of eight rows (1024
instructions) at a time, and to program one row or one
word at a time. Table 32-12 lists typical erase and pro-
gramming times. The 8-row erase pages and single
row write rows are edge-aligned from the beginning of
program memory, on boundaries of 3072 bytes and
384 bytes, respectively.
The program memory implements holding buffers,
which are located in the write latch area, that can
contain 128 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the buffers sequentially. The instruction
words loaded must always be from a group of 64
boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 128 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written. A programming cycle is required for
programming each row. For more information on eras-
ing and programming Flash memory, refer to Section
5. “Flash Programming” (DS70609) in the
“dsPIC33E/PIC24E Family Reference Manual”.
5.3 Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 32-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time and Word
Write Cycle Time parameters (see Table 32-12).
EQUATION 5-1: PROGRAMMING TIME
For example, if the device is operating at +125°C, the
FRC accuracy will be ±5%. If the TUN<5:0> bits (see
Register 9-4) are set to ‘b111111, the minimum row
write time is equal to Equation 5-2.
EQUATION 5-2: MINIMUM ROW WRITE
TIME
The maximum row write time is equal to Equation 5-3.
EQUATION 5-3: MAXIMUM ROW WRITE
TIME
Setting the WR bit (NVMCON<15>) starts the
operation, and the WR bit is automatically cleared
when the operation is finished.
T
7.37 MHz FRC Accuracy()% FRC Tuning()%××
----------------------------------------------------------------------------------------------------------------------------
T
RW
11064 Cycles
7.37 MHz 10.05+()1 0.00375–()××
------------------------------------------------------------------------------------------------
1.435ms==
T
RW
11064 Cycles
7.37 MHz 10.05–()1 0.00375–()××
------------------------------------------------------------------------------------------------
1.586ms==