Datasheet

PIC32MX5XX/6XX/7XX
DS61156G-page 92 © 2009-2011 Microchip Technology Inc.
34D0 DCH5DAT
31:16
0000
15:0
CHPDAT<7:0> 0000
34E0 DCH6CON
31:16
0000
15:0 CHBUSY
CHCHNS CHEN CHAED CHCHN CHAEN CHEDET CHPRI<1:0> 0000
34F0 DCH6ECON
31:16
CHAIRQ<7:0> 00FF
15:0
CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN FF00
3500 DCH6INT
31:16
CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
15:0
CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
3510 DCH6SSA
31:16
CHSSA<31:0>
0000
15:0 0000
3520 DCH6DSA
31:16
CHDSA<31:0>
0000
15:0 0000
3530 DCH6SSIZ
31:16
0000
15:0 CHSSIZ<15:0> 0000
3540 DCH6DSIZ
31:16
0000
15:0 CHDSIZ<15:0> 0000
3550 DCH6SPTR
31:16
0000
15:0 CHSPTR<15:0> 0000
3560 DCH6DPTR
31:16
0000
15:0 CHDPTR<15:0> 0000
3570 DCH6CSIZ
31:16
0000
15:0 CHCSIZ<15:0> 0000
3580 DCH6CPTR
31:16
0000
15:0 CHCPTR<15:0> 0000
3590 DCH6DAT
31:16
0000
15:0
CHPDAT<7:0> 0000
35A0 DCH7CON
31:16
0000
15:0 CHBUSY
CHCHNS CHEN CHAED CHCHN CHAEN CHEDET CHPRI<1:0> 0000
35B0 DCH7ECON
31:16
CHAIRQ<7:0> 00FF
15:0
CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN FF00
35C0 DCH7INT
31:16
CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
15:0
CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
35D0 DCH7SSA
31:16
CHSSA<31:0>
0000
15:0 0000
35E0 DCH7DSA
31:16
CHDSA<31:0>
0000
15:0 0000
TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP
(1,2)
(CONTINUED)
Virtual Address
(BF88_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.