Datasheet

PIC32MX5XX/6XX/7XX
DS61156G-page 66 © 2009-2011 Microchip Technology Inc.
10D0 IPC4
31:16
INT4IP<2:0> INT4IS<1:0> OC4IP<2:0> OC4IS<1:0> 0000
15:0
IC4IP<2:0> IC4IS<1:0> T4IP<2:0> T4IS<1:0> 0000
10E0 IPC5
31:16
OC5IP<2:0> OC5IS<1:0> 0000
15:0
IC5IP<2:0> IC5IS<1:0> T5IP<2:0> T5IS<1:0> 0000
10F0 IPC6
31:16
AD1IP<2:0> AD1IS<1:0> CNIP<2:0> CNIS<1:0> 0000
I2C1IP<2:0> I2C1IS<1:0>
U1IP<2:0> U1IS<1:0>
000015:0 SPI3IP<2:0> SPI3IS<1:0>
I2C3IP<2:0> I2C3IS<1:0>
1100 IPC7
U3IP<2:0> U3IS<1:0>
CMP2IP<2:0> CMP2IS<1:0> 000031:16 SPI2IP<2:0> SPI2IS<1:0>
I2C4IP<2:0> I2C4IS<1:0>
15:0
CMP1IP<2:0> CMP1IS<1:0> PMPIP<2:0> PMPIS<1:0> 0000
1110 IPC8
31:16
RTCCIP<2:0> RTCCIS<1:0> FSCMIP<2:0> FSCMIS<1:0> 0000
U2IP<2:0> U2IS<1:0>
000015:0 SPI4IP<2:0> SPI4IS<1:0>
I2C5IP<2:0> I2C5IS<1:0>
1120 IPC9
31:16
DMA3IP<2:0> DMA3IS<1:0> DMA2IP<2:0> DMA2IS<1:0> 0000
15:0
DMA1IP<2:0> DMA1IS<1:0> DMA0IP<2:0> DMA0IS<1:0> 0000
1130 IPC10
31:16
DMA7IP<2:0>
(2)
DMA7IS<1:0>
(2)
DMA6IP<2:0>
(2)
DMA6IS<1:0>
(2)
0000
15:0
DMA5IP<2:0>
(2)
DMA5IS<1:0>
(2)
DMA4IP<2:0>
(2)
DMA4IS<1:0>
(2)
0000
1140 IPC11
31:16
0000
15:0
USBIP<2:0> USBIS<1:0> FCEIP<2:0> FCEIS<1:0> 0000
1150 IPC12
31:16
U5IP<2:0> U5IS<1:0> U6IP<2:0> U6IS<1:0> 0000
15:0
U4IP<2:0> U4IS<1:0> ETHIP<2:0> ETHIS<1:0> 0000
TABLE 4-3: INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES
(1)
(CONTINUED)
Virtual Address
(BF88_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX664 devices.
3: This register does not have associated CLR, SET, and INV registers.