Datasheet

PIC32MX5XX/6XX/7XX
DS61156G-page 52 © 2009-2011 Microchip Technology Inc.
TABLE 3-2: COPROCESSOR 0 REGISTERS
Register
Number
Register
Name
Function
0-6 Reserved Reserved.
7 HWREna Enables access via the RDHWR instruction to selected hardware registers.
8 BadVAddr
(1)
Reports the address for the most recent address-related exception.
9 Count
(1)
Processor cycle count.
10 Reserved Reserved.
11 Compare
(1)
Timer interrupt control.
12 Status
(1)
Processor status and control.
12 IntCtl
(1)
Interrupt system status and control.
12 SRSCtl
(1)
Shadow register set status and control.
12 SRSMap
(1)
Provides mapping from vectored interrupt to a shadow set.
13 Cause
(1)
Cause of last general exception.
14 EPC
(1)
Program counter at last exception.
15 PRId Processor identification and revision.
15 EBASE Exception vector base register.
16 Config Configuration register.
16 Config1 Configuration Register 1.
16 Config2 Configuration Register 2.
16 Config3 Configuration Register 3.
17-22 Reserved Reserved.
23 Debug
(2)
Debug control and exception status.
24 DEPC
(2)
Program counter at last debug exception.
25-29 Reserved Reserved.
30 ErrorEPC
(1)
Program counter at last error.
31 DESAVE
(2)
Debug handler scratchpad register.
Note 1: Registers used in exception processing.
2: Registers used during debug.