Datasheet

PIC32MX5XX/6XX/7XX
DS61156G-page 38 © 2009-2011 Microchip Technology Inc.
PMA0 30 44 L8 I/O TTL/ST Parallel Master Port Address bit 0 input
(Buffered Slave modes) and output (Master
modes)
PMA1 29 43 K7 I/O TTL/ST Parallel Master Port Address bit 1 input
(Buffered Slave modes) and output (Master
modes)
PMA2 8 14 F3 O — Parallel Master Port address (Demultiplexed
Master modes)
PMA3 6 12 F2 O —
PMA4 5 11 F4 O —
PMA5 4 10 E3 O —
PMA6 16 29 K3 O —
PMA7 22 28 L2 O —
PMA8 32 50 L11 O —
PMA9 31 49 L10 O —
PMA10 28 42 L7 O —
PMA11 27 41 J7 O —
PMA12 24 35 J5 O —
PMA13 23 34 L5 O —
PMA14 45 71 C11 O —
PMA15 44 70 D11 O —
PMCS1 45 71 C11 O — Parallel Master Port Chip Select 1 strobe
PMCS2 44 70 D11 O — Parallel Master Port Chip Select 2 strobe
PMD0 60 93 A4 I/O TTL/ST Parallel Master Port data (Demultiplexed
Master mode) or address/data (Multiplexed
Master modes)
PMD1 61 94 B4 I/O TTL/ST
PMD2 62 98 B3 I/O TTL/ST
PMD3 63 99 A2 I/O TTL/ST
PMD4 64 100 A1 I/O TTL/ST
PMD5 1 3 D3 I/O TTL/ST
PMD6 2 4 C1 I/O TTL/ST
PMD7 3 5 D2 I/O TTL/ST
PMD8 — 90 A5 I/O TTL/ST
PMD9 — 89 E6 I/O TTL/ST
PMD10 — 88 A6 I/O TTL/ST
PMD11 — 87 B6 I/O TTL/ST
PMD12 — 79 A9 I/O TTL/ST
PMD13 — 80 D8 I/O TTL/ST
PMD14 — 83 D7 I/O TTL/ST
PMD15 — 84 C7 I/O TTL/ST
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
(1)
Pin
Type
Buffer
Type
Description
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.