Datasheet

PIC32MX5XX/6XX/7XX
DS61156G-page 198 © 2009-2011 Microchip Technology Inc.
FIGURE 31-4: POWER-ON RESET TIMING CHARACTERISTICS
VDD
VPOR
Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(V
DD < VDDMIN).
2: Includes interval voltage regulator stabilization delay.
SY00
Power-up Sequence
(Note 2)
Internal Voltage Regulator Enabled
(TPU)
SY10
CPU Starts Fetching Code
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR
SY00
Power-up Sequence
(Note 2)
Internal Voltage Regulator Enabled
(TPU)
(T
SYSDLY)
CPU Starts Fetching Code
(Note 1)
(Note 1)
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
(TOST)
SY02
(T
SYSDLY)
SY02