Datasheet

PIC32MX5XX/6XX/7XX
DS61156G-page 138 © 2009-2011 Microchip Technology Inc.
FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)
(1)
TMRy
TMRx
TyIF Event
Equal
32-bit Comparator
PRy
PRx
Reset
LS Half Word
MS Half Word
Flag
Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use
of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
2: TxCK pins are not available on 64-pin devices.
3: ADC event trigger is available only on the Timer2/3 pair.
TGATE (TxCON<7>)
0
1
PBCLK
Gate
TxCK
(2)
Sync
Sync
ADC Event
Trigger
(3)
ON (TxCON<15>)
TGATE (TxCON<7>)
TCS (TxCON<1>)
TCKPS (TxCON<6:4>)
Prescaler
3
1, 2, 4, 8, 16,
32, 64, 256
1 0
0 0
Q
Q
D
x 1