Datasheet

© 2009-2011 Microchip Technology Inc. DS61156G-page 101
PIC32MX5XX/6XX/7XX
TABLE 4-34: PORTG REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
(1)
Virtual Address
(BF88_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6180
TRISG
31:16
— — — — — — — — — — — — — — — — 0000
15:0
— — — — — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 — — 03CC
6190 PORTG
31:16
— — — — — — — — — — — — — — — — 0000
15:0
— — — — — — RG9 RG8 RG7 RG6 — — RG3 RG2 — — xxxx
61A0 LATG
31:16
— — — — — — — — — — — — — — — — 0000
15:0
— — — — — — LATG9 LATG8 LATG7 LATG6 — —LATG3LATG2— — xxxx
61B0 ODCG
31:16
— — — — — — — — — — — — — — — — 0000
15:0
— — — — — — ODCG9 ODCG8 ODCG7 ODCG6 — — ODCG3 ODCG2 — — 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-35: PORTG REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
(1)
Virtual Address
(BF88_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
6180 TRISG
31:16
— — — — — — — — — — — — — — — — 0000
15:0 TRISG15 TRISG14 TRISG13 TRISG12
— — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 F3CF
6190 PORTG
31:16
— — — — — — — — — — — — — — — — 0000
15:0 RG15 RG14 RG13 RG12
— — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 xxxx
61A0 LATG
31:16
— — — — — — — — — — — — — — — — 0000
15:0 LATG15 LATG14 LATG13 LATG12
— — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 xxxx
61B0 ODCG
31:16
— — — — — — — — — — — — — — — — 0000
15:0 ODCG15 ODCG14 ODCG13 ODCG12
— — ODCG9 ODCG8 ODCG7 ODCG6 — — ODCG3 ODCG2 ODCG1 ODCG0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.