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PIC32MX5XX/6XX/7XX

Family Data Sheet

High-Performance, USB, CAN and Ethernet

32-bit Flash Microcontrollers

Summary of content (256 pages)

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PIC32MX5XX/6XX/7XX Family Data Sheet High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers © 2009-2011 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC32MX5XX/6XX/7XX High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers High-Performance 32-bit RISC CPU: Peripheral Features (Continued): • MIPS32® M4K® 32-bit core with 5-stage pipeline • 80 MHz maximum frequency • 1.56 DMIPS/MHz (Dhrystone 2.
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PIC32MX5XX/6XX/7XX TABLE 1: PIC32 USB AND CAN – FEATURES Device Pins Program Memory (KB) Data Memory (KB) USB CAN Timers/Capture/Compare DMA Channels (Programmable/ Dedicated) UART(2,3) SPI(3) I2C™(3) 10-bit 1 Msps ADC (Channels) Comparators PMP/PSP JTAG Trace Packages(4) USB and CAN PIC32MX534F064H 64 64 + 12(1) 16 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX564F064H 64 64 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX564F128H 64
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PIC32MX5XX/6XX/7XX TABLE 2: PIC32 USB AND ETHERNET – FEATURES Device Pins Program Memory (KB) Data Memory (KB) USB Ethernet Timers/Capture/Compare DMA Channels (Programmable/ Dedicated) UART(2,3) SPI(3) I2C™(3) 10-bit 1 Msps ADC (Channels) Comparators PMP/PSP JTAG Trace Packages(4) USB and Ethernet PIC32MX664F064H 64 64 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX664F128H 64 128 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32
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PIC32MX5XX/6XX/7XX TABLE 3: PIC32 USB, ETHERNET AND CAN – FEATURES Pins Program Memory (KB) Data Memory (KB) USB Ethernet CAN Timers/Capture/Compare DMA Channels (Programmable/ Dedicated) UART(2,3) SPI(3) I2C™(3) 10-bit 1 Msps ADC (Channels) Comparators JTAG Trace Packages(4) PIC32MX764F128H 64 128 + 12(1) 32 1 1 1 5/5/5 4/6 6 3 4 16 2 Yes Yes No PT, MR PIC32MX775F256H 64 256 + 12(1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT, MR PIC32MX775F512H 64 512
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PIC32MX5XX/6XX/7XX Pin Diagrams 64-Pin QFN(1) PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 C1TX/RF1 C1RX/RF0 VDD VCAP/VCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 SCK3/U4TX/U1RTS/OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/
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PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN(1) ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0 VDD VCAP/VCORE ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/R
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PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN(1) ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 PIC32MX775F256H 8 40 PIC32MX775F512H 9 39 PIC32MX795F512H 10 38 11 37 12 36 13 35 1
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PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN(1) ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 PIC32MX764F128H 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22
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PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) = Pins are up to 5V tolerant PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 C1TX/RF1 C1RX/RF0 VDD VCAP/VCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 SCK3/U4TX/U1RTS/OC2/RD1 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN
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PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0 VDD VCAP/VCORE ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 ERXERR/PMD4/RE4 ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN
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PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 PIC32MX775F256H 9 PIC32MX775F512H 10 PIC32MX795F512H 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 EC
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PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 PIC32MX764F128H 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/
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PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L PIC32MX575F512L PIC32MX575F256L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/IC1/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 S
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PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 ETXERR/PMD9/RG1 ETXD0/PMD10/RF1 ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PIC32MX664F064L PIC32MX664F128L PIC32MX675F256L PIC32MX675F512L PIC32MX695F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PIC32MX775F256L PIC32MX775F512L PIC32MX795F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DS61156G-page 17 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 VSS VDD TCK/RA1 AC1TX/SCK4/U5TX/U2RTS/RF13 AC1RX/SS4/U5RX/U2CTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1
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PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 ETXERR/PMD9/RG1 C1TX/ETXD0/PMD10/RF1 C1RX/ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PIC32MX764F128L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 1
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PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 121-Pin XBGA(1) = Pins are up to 5V tolerant PIC32MX534F064L PIC32MX564F064L PIC32MX664F064L PIC32MX564F128L PIC32MX664F128L PIC32MX764F128L PIC32MX575F256L PIC32MX675F256L PIC32MX775F256L PIC32MX575F512L PIC32MX675F512L PIC32MX695F512L PIC32MX775F512L PIC32MX795F512L A B C D E F G H J K L 1 2 3 4 5 6 7 8 9 10 11 RE4 RE3 RG13 RE0 RG0 RF1 VDD VSS RD12 RD2 RD1 NC RG15 RE2 RE1 RA7 RF0 VCAP/ VCORE RD5 RD3 VSS RC14 RE6 VDD RG12
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PIC32MX5XX/6XX/7XX TABLE 4: PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L AND PIC32MX575F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 C1TX/PMD10/RF1 F2 SCL4/SDO2/U3TX/PMA3/CN10/RG8 A7 VDD F3 SS2/U6RX/U3CTS/PMA2/CN11/RG9 A8 VSS F4 SDA4/SDI2/U3RX/PMA4/CN9/RG7 A9 IC5/PMD12/RD12 F5 V
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PIC32MX5XX/6XX/7XX TABLE 4: PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 AC1RX/SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS/RF13 K8 VDD L7 AN13/PMA10/RB13 K9 SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15 K10 USBID/RF3 L9 SS3/U
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PIC32MX5XX/6XX/7XX TABLE 5: PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 A2 PMD3/RE3 E9 AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/AEMDIO/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV//SCL4/SDO2/ U3TX/PMA3/CN10/RG8 A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK//SS2/U6
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PIC32MX5XX/6XX/7XX TABLE 5: PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 SCK4/U5TX/U2RTS/RF13 K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN1
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PIC32MX5XX/6XX/7XX TABLE 6: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14 A5 C2RX/PMD8/RG0 F1 MCLR A6 C1TX/ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/ U3TX/PMA3/CN10/RG8 A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/ U3CTS/PMA2/CN11/RG9
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PIC32MX5XX/6XX/7XX TABLE 6: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 K5 No Connect (NC) L4 AVSS AN9/C2OUT/RB9 K6 AC1RX/SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS/RF13 K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 K10 USBID/RF3
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PIC32MX5XX/6XX/7XX TABLE 7: PIN NAME: PIC32MX764F128L DEVICE Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 C1TX/ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/ U3TX/PMA3/CN10/RG8 A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/ U3CTS/PMA2/CN11/RG9 A8 VSS F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG
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PIC32MX5XX/6XX/7XX TABLE 7: PIN NAME: PIC32MX764F128L DEVICE (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 K5 No Connect (NC) L4 AVSS AN9/C2OUT/RB9 K6 AC1RX/SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS/RF13 K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 K10 USBID/RF3 L9 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 K
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PIC32MX5XX/6XX/7XX Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 31 2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 43 3.0 CPU........................................................................................................
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PIC32MX5XX/6XX/7XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
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PIC32MX5XX/6XX/7XX 1.0 DEVICE OVERVIEW This document contains device-specific information for PIC32MX5XX/6XX/7XX devices. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number(1) Pin Type Buffer Type K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 I I I I I I I I I I I Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog 35 41 42 43 44 63 J5 J7 L7 K7 L8 F9 I I I I I I 40 64 F11 O OSC1 39 63 F9 I OSC2 40 64 F11 I/O SOSCI 47 73 C10 I Pin Name 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 16 15 14 13 12 11 17 18 21 22 23 25 24 23 22 21
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PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 IC1 IC2 IC3 IC4 IC5 OCFA OC1 OC2 OC3 OC4 OC5 OCFB INT0 INT1 INT2 INT3 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 32 — — — 42 43 44 45 52 17 46 49 50 51 52 30 46 42 43 44 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 50 80 47 48 68 69 70 71 79 26 72 76 77 78 8
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PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA Pin Type Buffer Type Description RA0 — 17 G3 I/O ST PORTA is a bidirectional I/O port RA1 — 38 J6 I/O ST RA2 — 58 H11 I/O ST RA3 — 59 G10 I/O ST RA4 — 60 G11 I/O ST RA5 — 61 G9 I/O ST RA6 — 91 C5 I/O ST RA7 — 92 B5 I/O ST RA9 — 28 L2 I/O ST RA10 — 29 K3 I/O ST RA14 — 66 E11 I/O ST RA15 — 67 E8 I/O ST RB0 16 25 K2 I/O ST PORTB is a bidirectional I/O port RB1 15 24 K1 I/O
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PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA Pin Type Buffer Type Description RD0 46 72 D9 I/O ST PORTD is a bidirectional I/O port RD1 49 76 A11 I/O ST RD2 50 77 A10 I/O ST RD3 51 78 B9 I/O ST RD4 52 81 C8 I/O ST RD5 53 82 B8 I/O ST RD6 54 83 D7 I/O ST RD7 55 84 C7 I/O ST RD8 42 68 E9 I/O ST RD9 43 69 E10 I/O ST RD10 44 70 D11 I/O ST RD11 45 71 C11 I/O ST RD12 — 79 A9 I/O ST RD13 — 80 D8 I/O ST RD14 — 47 L9 I/O S
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PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST L9 I ST UART1 clear to send K9 K11 O — UART1 ready to send I ST UART1 receive O — UART1 transmit I ST UART3 clear to send E3 F4 O — UART3 ready to send I ST UART3 receive 12 F2 O — UART3 transmit 21 40 K6 I ST UART2 clear to send 39 49 L6 L10 O — UART2 ready to
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PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type Description E10 K9 K11 J10 I/O I/O I O ST ST ST — SPI1 slave synchronization or frame pulse I/O Synchronous serial clock input/output for SPI3 SPI3 data in SPI3 data out 47 10 11 12 L9 E3 F4 F2 I/O I/O I O ST ST ST — SPI3 slave synchronization or frame pulse I/O Synchronous serial clock input/output for SPI2 SPI2 data in SPI2 data out 8 29 31 32 14 39 49 50 F3 L6 L10 L11 I/O I/O I O ST ST S
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PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name Pin Type Buffer Type L8 I/O TTL/ST 43 K7 I/O TTL/ST 14 12 11 10 29 28 50 49 42 41 35 34 71 70 71 70 F3 F2 F4 E3 K3 L2 L11 L10 L7 J7 J5 L5 C11 D11 C11 D11 O O O O O O O O O O O O O O O O — — — — — — — — — — — — — — — — 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA PMA0 30 44 PMA1 29 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 PMCS1 PMCS2 8 6 5 4 16 22 32 31 28 27 24 23
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PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type L8 O — 43 K7 O — 53 52 34 35 82 81 54 55 B8 C8 H8 H9 O O I P — — Analog — VBUSON D+ DUSBID C1RX C1TX AC1RX AC1TX C2RX C2TX AC2RX AC2TX ERXD0 ERXD1 ERXD2 11 37 36 33 58 59 32 31 29 21 — — 61 60 59 20 57 56 51 87 88 40 39 90 89 8 7 41 42 43 H1 H10 J11 K10 B6 A6 K6 L6 A5 E6 E2 E4 J7 L7 K7 O I/O I/O I I O I O I O 1 O I I I — Analog Analog ST ST — ST — ST — ST — ST ST ST ERXD3 ERXERR ERXDV E
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PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type C11 O — Ethernet management data clock(2) 68 18 19 28 29 1 12 12 14 14 E9 G1 G2 L2 K3 B2 F2 F2 F3 F3 I/O I I I I I I I I I — ST ST ST ST ST ST ST ST ST Ethernet management data(2) Alternate Ethernet Receive Data 0(2) Alternate Ethernet Receive Data 1(2) Alternate Ethernet Receive Data 2(2) Alternate Ethernet Receive Data 3(2) Alternate Ethernet receive error input(2) Alternate Ethernet receive da
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PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name AVDD 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA 19 30 J4 Buffer Type P P Description Positive supply for analog modules. This pin must be connected at all times.
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PIC32MX5XX/6XX/7XX 2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic CBP R1 MCLR C VSS VCAP/VCORE R VDD CEFC VDD PIC32 VSS 10 Ω 2.2.1 VDD 0.1 µF Ceramic CBP VSS VDD AVSS VDD AVDD 0.1 µF Ceramic CBP VSS 0.1 µF Ceramic CBP 0.1 µF Ceramic CBP BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 µF to 47 µF. This capacitor should be located as close to the device as possible. 2.3 2.3.1 2.
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PIC32MX5XX/6XX/7XX 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
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PIC32MX5XX/6XX/7XX 2.8 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator. Refer to Section 8.0 “Oscillator Configuration” for details. The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them.
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PIC32MX5XX/6XX/7XX 2.11 Referenced Sources This device data sheet is based on the following individual chapters of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the PIC32MX795F512L product page on the Microchip web site (www.microchip.com) or select a family reference manual section from the following list.
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PIC32MX5XX/6XX/7XX CPU Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS61113) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32® M4K® Processor Core are available at http://www.mips.com.
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PIC32MX5XX/6XX/7XX 3.2 Architecture Overview The MIPS® M4K® processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: • • • • • • • • Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller 3.2.
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PIC32MX5XX/6XX/7XX TABLE 3-1: MIPS® M4K® CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate MULT/MULTU, MADD/MADDU, MSUB/MSUBU 16 bits 1 1 32 bits 2 2 MUL 16 bits 2 1 DIV/DIVU 32 bits 3 2 8 bits 12 11 16 bits 19 18 24 bits 26 25 32 bits 33 32 The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers.
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PIC32MX5XX/6XX/7XX TABLE 3-2: Register Number 0-6 COPROCESSOR 0 REGISTERS Register Name Reserved Function Reserved. 7 HWREna Enables access via the RDHWR instruction to selected hardware registers. 8 BadVAddr(1) Reports the address for the most recent address-related exception. 9 Count(1) Processor cycle count. 10 Reserved (1) Reserved. 11 Compare 12 Status(1) Timer interrupt control. Processor status and control. 12 IntCtl(1) Interrupt system status and control.
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PIC32MX5XX/6XX/7XX Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. TABLE 3-3: PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES Exception Reset Description Assertion MCLR or a Power-on Reset (POR). DSS EJTAG debug single step. DINT EJTAG debug interrupt.
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PIC32MX5XX/6XX/7XX 3.3 Power Management The MIPS M4K Processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or Halting the clocks, which reduces system power consumption during Idle periods. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking Power-Down mode is through execution of the WAIT instruction.
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PIC32MX5XX/6XX/7XX 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. For detailed information, refer to Section 3. “Memory Organization” (DS61115) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB of unified virtual memory address space.
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PIC32MX5XX/6XX/7XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX564F064H, PIC32MX564F064L, PIC32MX664F064H AND PIC32MX664F064L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD010000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC
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PIC32MX5XX/6XX/7XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX534F064H AND PIC32MX534F064L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD010000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0004000 Reserved 0xA0003FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Configura
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PIC32MX5XX/6XX/7XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L, PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND PIC32MX764F128L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD020000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0xA0
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PIC32MX5XX/6XX/7XX FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L, PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND PIC32MX775F256L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD040000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0010000 Reserved 0xA000FFFF RAM(2) 0xA0
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PIC32MX5XX/6XX/7XX FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L, PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND PIC32MX775F512L DEVICES Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD080000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0010000 Reserved 0xA000FFFF RAM(2) 0xA0000
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PIC32MX5XX/6XX/7XX FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L, PIC32MX795F512H AND PIC32MX795F512L DEVICES Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD080000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0020000 Reserved 0xA001FFFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02F
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Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 31:16 — — — — — BMXCHEDMA — — 15:0 — — — — — — — — 31:16 2010 BMXDKPBA(1) 15:0 — — — — — — — — 31:16 2020 BMXDUDBA(1) 15:0 — — — — — — — — 31:16 2030 BMXDUPBA(1) 15:0 — — — — — — — — 2040 BMXDRMSZ 2060 BMXPFMSZ 2070 BMXBOOTSZ 15:0 31:16 15:0 21/5 19/3 18/2 17/1 16/0 — — — — BMXWSDRM — — — — — — — — — — — 0000 — — — — — — 0000 — — — — — — 0000 BMXERRIXI BMXER
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INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND PIC32MX575F512H DEVICES(1) INTCON 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 DS61156G-page 63 10A0 IPC1 30/14 29/13 28/12 27/11 26/10 — 31:16 — — — — — 15:0 — FRZ — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — — INT4EP — — — — — — TPC<2:0> — — — SRIPL<2:0>
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INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND PIC32MX575F512H DEVICES(1) (CONTINUED) IPC2 10C0 IPC3 10D0 IPC4 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 © 2009-2011 Microchip Technology Inc.
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Virtual Address (BF88_#) Register Name 1000 INTCON 1010 INTSTAT(3) INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES(1) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 10A0 IPC1 10B0 IPC2 DS61156G-page 65 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 — 31:16 — — — — — 15:0 — FRZ — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — —
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Virtual Address (BF88_#) Register Name 10D0 IPC4 10E0 IPC5 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 Legend: 31/15 30/14 29/13 31:16 — — — INT4IP<2:0> 15:0 — — — IC4IP<2:0> 31:16 — — — 15:0 — — — IC5IP<2:0> 31:16 — — — AD1IP<2:0> 15:0 31:16 — — — — 28/12 — — 27/11 — 26/10 — I2C1IP<2:0> — 25/9 23/7 22/6 21/5 INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000 — — — O
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Virtual Address (BF88_#) Register Name 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 10A0 IPC1 DS61156G-page 67 10B0 IPC2 IPC3 10C0 30/14 29/13 28/12 27/11 26/10 — 31:16 — — — — — 15:0 — FRZ — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — — SS
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Virtual Address (BF88_#) Register Name 10D0 IPC4 10E0 IPC5 INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) (CONTINUED) 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0
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Virtual Address (BF88_#) Register Name 1000 INTCON 1010 INTSTAT(3) INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND PIC32MX575F256L DEVICES(1) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 10A0 IPC1 DS61156G-page 69 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 — 31:16 — — — — — 15:0 — FRZ — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — — —
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Virtual Address (BF88_#) Register Name 10D0 IPC4 INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND PIC32MX575F256L DEVICES(1) (CONTINUED) 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 — — — INT4IP<2:0> 15:0 — — — IC4IP<2:0> 31:16 — — — 15:0 — — 31:16 — — 15:0 31:16 — — — — 28/12 23/7 22/6 21/5 INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 IC4
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Virtual Address (BF88_#) Register Name 1000 INTCON 1010 INTSTAT(3) INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES(1) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 10A0 IPC1 DS61156G-page 71 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 — 31:16 — — — — — 15:0 — FRZ — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — —
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Virtual Address (BF88_#) Register Name 10D0 IPC4 10E0 IPC5 INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES(1) (CONTINUED) 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 15:0 — — — IC4IP<2:0> IC4IS<1:0>
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Virtual Address (BF88_#) Register Name 1000 INTCON 1010 INTSTAT(3) INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 10A0 IPC1 DS61156G-page 73 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 — 31:16 — — — — — 15:0 — FRZ — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — —
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Virtual Address (BF88_#) Register Name 10D0 IPC4 10E0 IPC5 INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED) 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 — — — INT4IP<2:0> 15:0 — — — IC4IP<2:0> 31:16 — — — 15:0 — — 31:16 — — 15:0 31:16 — — — — 23/7 22/6 21/5 INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 IC4IS<1:0> — — — T4IP<
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Virtual Address (BF80_#) 0600 T1CON 0610 TMR1 0620 TMR2 0820 TMR3 TMR5 PR5 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — 0000 FRZ SIDL TWDIS TWIP — — — TGATE — TCKPS<1:0> — TSYNC TCS — 0000 31:16 — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 15:0 TMR1<15:0> — — — — — — — — 31:16 — — — — — — — — — — 15:0 ON FRZ SIDL — — — — — TGATE 31:16 — — — — —
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Virtual Address (BF80_#) Register Name 2000 IC1CON(1) 2010 IC1BUF 2200 IC2CON(1) 2210 IC2BUF 2400 IC3CON(1) 2410 IC3BUF 2600 IC4CON(1) 2610 IC4BUF 2800 IC5CON(1) 2810 IC5BUF INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 — — 31:16 — — — — — — — — — 15:0 ON FRZ SIDL — — — FEDGE C32 ICTMR 31:16 15:0 — — — — — — — — — 15:0 ON FRZ SIDL — — — FEDGE C32 ICTMR 31:16 18/2 — — —
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Virtual Address (BF80_#) 3000 OC1CON 3010 OC1R 3020 OC1RS 3200 OC2CON 3210 OC2R 3220 OC2RS 3400 OC3CON 3410 OC3R 3420 OC3RS 3610 OC4R 3620 OC4RS 3800 OC5CON 3810 OC5R 3820 OC5RS 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 — 31:16 — — — — — — — — — — — — — 15:0 ON FRZ SIDL — — — — — — — OC32 OCFLT OCTSEL 31:16 31:16 xxxx xxxx — — — — — — — — — — — — 15:0 ON FRZ SIDL — — — — — — — OC32 OCFLT OCT
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Virtual Address (BF80_#) Register Name 5000 I2C3CON I2C3STAT 5020 I2C5DD 5030 I2C3MSK 5040 I2C3BRG 5050 I2C3TRN 5060 I2C3RCV 5100 I2C4CON © 2009-2011 Microchip Technology Inc.
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Virtual Address (BF80_#) Register Name 5220 I2C5ADD 5230 I2C5MSK 5240 I2C5BRG 5250 I2C5TRN 5260 I2C5RCV 5300 I2C1CON I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP(1) (CONTINUED) I2C1STAT 5320 I2C3DD 5330 I2C1MSK 5340 I2C1BRG 5350 I2C1TRN 5360 I2C1RCV 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 15:0 — — — — — — 31:16 — — — — — — 15:0 — — — — — — 31:16 — — — —
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Virtual Address (BF80_#) 5410 I2C2STAT I2C4DD 5430 I2C2MSK 5440 I2C2BRG 5450 I2C2TRN 5460 I2C2RCV 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name Bits 5400 I2C2CON 5420 I2C2 REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND
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Virtual Address (BF80_#) U1STA(1) 6010 U1TXREG 6030 U1RXREG 6040 U1BRG(1) 6200 U4MODE U4STA(1) 6210 6220 (1) U4TXREG U4RXREG 6240 U4BRG(1) 6400 U3MODE(1) 6410 U3STA(1) 6420 U3TXREG 6430 U3RXREG 6440 (1) U3BRG DS61156G-page 81 6600 U6MODE(1) 6610 U6STA(1) 6620 U6TXREG 30/14 29/13 28/12 27/11 26/10 25/9 24/8 — — 31:16 — — — — — — 15:0 ON FRZ SIDL IREN RTSMD — 31:16 — — 15:0 UTXISEL<1:0> 31:16 — UEN<1:0> — — — — — ADM_EN UTXINV URXEN UTXBR
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Virtual Address (BF80_#) Register Name 6630 U6RXREG 6640 U6BRG(1) UART1 THROUGH UART6 REGISTER MAP (CONTINUED) 6800 U2MODE(1) 6810 U2STA(1) 6820 U2TXREG 6830 U2RXREG 6840 U2BRG(1) 6A00 U5MODE(1) 6A10 U5STA(1) 6A20 U5TXREG 6A30 U5RXREG 6A40 U5BRG(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — 15:0 — — — — — — — — — — — — RX8 31:16 — — — — — — — — 31:16 — — — — — — — — 15:0 ON FRZ SIDL IREN RTSMD
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Virtual Address (BF80_#) 5800 SPI3CON 5810 SPI3STAT 5820 SPI3BUF 5830 SPI3BRG 5A00 SPI2CON 5A10 SPI2STAT 5A20 SPI2BUF 5A30 SPI2BRG 5C00 SPI4CON 5C20 SPI4BUF 5C30 SPI4BRG 30/14 29/13 31:16 FRMEN 15:0 ON FRMSYNC FRMPOL FRZ SIDL 31:16 — — — 15:0 — — — 28/12 27/11 26/10 MSSEN FRMSYPW DISSDO MODE32 25/9 24/8 23/7 — CKE SSEN — — — SRMT SPIROV SPIRBE FRMCNT<2:0> MODE16 SMP RXBUFELM<4:0> — SPIBUSY — — 31:16 SPITUR 22/6 21/5 20/4 19/3 18/2 17/1 — — CKP MST
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5E10 SPI1STAT SPI1BUF 5E30 SPI1BRG 31/15 30/14 29/13 31:16 FRMEN 15:0 ON FRMSYNC FRMPOL FRZ SIDL 31:16 — — — 15:0 — — — 28/12 27/11 26/10 MSSEN FRMSYPW DISSDO MODE32 25/9 24/8 23/7 — CKE SSEN — — — SRMT SPIROV SPIRBE FRMCNT<2:0> MODE16 SMP RXBUFELM<4:0> — SPIBUSY — — 31:16 SPITUR 22/6 21/5 20/4 19/3 18/2 17/1 — — CKP MSTEN — — — SPIFE — STXISEL<1:0> 16/0 ENHBUF 0000 SRXISEL<1:0> TXBUFELM<4:0> — SPITBE — 31:16 — — — — — — — 15:0 — —
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ADC REGISTER MAP Register Name 9000 AD1CON1(1) 9010 AD1CON2(1) 9020 AD1CON3(1) 9040 AD1CHS(1) 9060 AD1PCFG(1) 9050 AD1CSSL (1) 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90B0 ADC1BUF4 90C0 ADC1BUF5 90D0 ADC1BUF6 90E0 ADC1BUF7 90F0 ADC1BUF8 9100 ADC1BUF9 DS61156G-page 85 9110 ADC1BUFA 9120 ADC1BUFB 30/14 29/13 28/12 27/11 26/10 — 25/9 24/8 23/7 — — — 22/6 21/5 — — 31:16 — — — — — 15:0 ON FRZ SIDL — — 31:16 — — — — — — — — — — FORM<2:0> 15:0 VCFG2 VCFG1 VC
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Register Name 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 9160 ADC1BUFF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ADC Result Word E (ADC1BUFE<31:0>) ADC Result Word F (ADC1BUFF<31:0>) Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
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Virtual Address (BF88_#) 3000 DMACON(1) DMASTAT 3020 DMAADDR 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — 31:16 — — — 15:0 ON FRZ — 31:16 — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — RDWR SUSPEND DMABUSY 31:16 DMACH<2:0>(2) 0000 DMAADDR<31:0> 15:0 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’.
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Virtual Address (BF88_#) 3070 DCH0ECON 3080 DCH0INT 3090 DCH0SSA 30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 30F0 DCH0CSIZ 3100 DCH0CPTR DCH0DAT 3120 DCH1CON © 2009-2011 Microchip Technology Inc.
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Virtual Address (BF88_#) DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED) 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON DCH2INT 3210 DCH2SSA 3220 DCH2DSA 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR 3260 DCH2DPTR 3270 DCH2CSIZ DS61156G-page 89 3280 DCH2CPTR 31:16 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — 15:0 31:16 — — — — — — — 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — —
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Virtual Address (BF88_#) Register Name 3290 DCH2DAT 32B0 DCH3ECON DCH3INT 32D0 DCH3SSA 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ 3340 DCH3CPTR 3350 DCH3DAT © 2009-2011 Microchip Technology Inc.
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Virtual Address (BF88_#) 33B0 DCH4SSIZ 33C0 DCH4DSIZ 33D0 DCH4SPTR 33E0 DCH4DPTR 33F0 DCH4CSIZ 3400 DCH4CPTR 3410 DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED) DCH4DAT 3420 DCH5CON 3430 DCH5ECON DCH5INT 3450 DCH5SSA 3460 DCH5DSA 3470 DCH5SSIZ 3480 DCH5DSIZ 3490 DCH5SPTR 34A0 DCH5DPTR DS61156G-page 91 34B0 DCH5CSIZ 34C0 DCH5CPTR 31:16 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — 0000 — — — — —
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Virtual Address (BF88_#) 34E0 DCH6CON 34F0 DCH6ECON 3500 DCH6INT 3510 DCH6SSA 3520 DCH6DSA 3530 DCH6SSIZ 3540 DCH6DSIZ 3550 DCH6SPTR 3560 DCH6DPTR 3570 DCH6CSIZ 3580 DCH6CPTR DCH6DAT © 2009-2011 Microchip Technology Inc.
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Virtual Address (BF88_#) 35F0 DCH7SSIZ 3600 DCH7DSIZ 3610 DCH7SPTR 3620 DCH7DPTR 3630 DCH7CSIZ 3640 DCH7CPTR 3650 DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED) DCH7DAT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — 15:0 31:16 — — — — — — — — — — — — — — 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — —
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Virtual Address (BF80_#) A000 CM1CON A010 CM2CON A060 CMSTAT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 — 31:16 — — — — — — — — 15:0 ON COE CPOL — — — — COUT 31:16 — — — — — — — — 15:0 ON COE CPOL — — — — COUT 31:16 — — — — — — — 15:0 — FRZ SIDL — — — — 20/4 19/3 18/2 17/1 16/0 — — — — — — — EVPOL<1:0> — CREF — — — CCH<1:0> — — All Resets Register Name Bit Range Bits 0000 00C3 — — — — — EVPOL<1:
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Virtual Address (BF80_#) FLASH CONTROLLER REGISTER MAP F410 NVMKEY F420 NVMADDR(1) F430 NVMDATA F440 NVMSRC ADDR 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — 31:16 — — — — — — — — — — — — 15:0 WR WREN WRERR LVDERR LVDSTAT — — — — — — — 31:16 NVMOP<3:0> 0000 0000 NVMKEY<31:0> 15:0 31:16 0000 0000 NVMADDR<31:0> 15:0 31:16 0000 0000 NVMDATA<31:0> 15:0 31:16 0000 0000 NVMSRCADDR<31:0> 15:0 0000 Legen
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Virtual Address (BF88_#) Register Name 6000 TRISA 6010 PORTA 6020 LATA 6030 ODCA PORTA REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — —
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Virtual Address (BF88_#) Register Name 6080 TRISC PORTC 60A0 LATC 60B0 ODCC 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — — — — — — F000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 RC15 RC14 RC13 RC12 — — — — — — — — — — — — xxxx 31:16 — — — — — — — — — — — — — — — —
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Virtual Address (BF88_#) Register Name 60C0 TRISD 60D0 PORTD 60E0 LATD 60F0 ODCD PORTD REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31/15 30/14 29/13 28/12 31:16 — — — — — — — — — — — — — — — — 0000
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Virtual Address (BF88_#) Register Name 6100 TRISE PORTE REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) 6110 PORTE 6120 LATE 6130 ODCE 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — — — — — — — — — — 15:0
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Virtual Address (BF88_#) Register Name 6140 TRISF PORTF REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) 6150 PORTF 6160 LATF 6170 ODCF 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — 15:0 — — — — — — — — — — TRISF5 31:16 —
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Virtual Address (BF88_#) Register Name 6180 TRISG 6190 PORTG 61A0 LATG ODCG 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 31:16 — — — — — — — — 15:0 — — — — — — TRISG9 TRISG8 — — — — TRISG7 TRISG6 — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — RG9 RG8 RG7 RG6 — 31:16 — — — — — — — — — — 15:0 — — — — — — LATG9 LATG8 LATG7 31:16 — — — — — — — — 15:0 — — — — — — ODCG9 ODCG8 19/3 18/2 1
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Virtual Address (BF88_#) CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES(1) 61C0 CNCON 61D0 CNEN 61E0 CNPUE 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — —
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Virtual Address (BF80_#) Register Name 7000 PMCON 7010 PMMODE 7020 PMADDR 7030 PMDOUT PMDIN 7050 PMAEN 7060 PMSTAT 30/14 29/13 31:16 — — — 15:0 ON FRZ SIDL 31:16 — — — 15:0 BUSY 31:16 — IRQM<1:0> — — 28/12 27/11 — — ADRMUX<1:0> — — INCM<1:0> — — 26/10 25/9 24/8 23/7 22/6 — — — — — PMPTTL PTWREN PTRDEN — — — MODE16 — — MODE<1:0> — — — — 20/4 19/3 18/2 17/1 16/0 — — — — — — ALP CS2P CS1P — WRSP RDSP 0000 — — — — — — 0000 — —
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Virtual Address (BF88_#) 4010 CHEACC(1) CHETAG(1) 4030 CHEMSK(1) 4040 CHEW0 4050 CHEW1 4060 CHEW2 4070 CHEW3 4080 CHELRU 4090 CHEHIT 40A0 CHEMIS 40C0 CHEPFABT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — — — — — — — — — 15:0 — — — — — — — 31:16 CHEWEN — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — 31:16 LTAGBOOT 15:0 31:16 DCSZ<1:0> — 15:0 15:0 31:16 15:0 15:0 — — — PREFEN<1:0> — — — — — —
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Virtual Address (BF80_#) Register Name 0200 RTCCON 0210 RTCALRM 0220 RTCTIME 0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — 15:0 ON FRZ SIDL — — — — — — — — — 31:16 — — — — 15:0 ALRMEN CHIME PIV ALRMSYNC HR01<3:0> 15:0 SEC10<3:0> SEC01<3:0> 31:16 YEAR10<3:0> YEAR01<3:0> 15:0 DAY10<3:0> DAY01<3:0> 31:16 HR10<3:0> HR01<3:0> 15:0 SEC10<3:0> — — — DAY10<3:0> — — 20/4 19/3
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2FF0 DEVCFG3 2FF4 DEVCFG2 2FF8 DEVCFG1 2FFC DEVCFG0 Legend: 31/15 30/14 31:16 FVBUSIO FUSBIDIO 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 — — — FCANIO FETHIO FMIIEN — — — — — FSRSSEL<2:0> — — — — FPLLODIV<2:0> xxxx — FPLLIDIV<2:0> xxxx 15:0 18/2 17/1 16/0 xxxx USERID<15:0> 31:16 — — — — — 15:0 UPLLEN — — — — 31:16 — — — — — — 15:0 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC 31:16 — — — — — — — — 15:0 — All Resets Bit Range
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Virtual Address (BF88_#) Register Name 5040 U1OTGIR(2) 5050 U1OTGIE 5070 U1OTGCON 5080 U1PWRC 5200 U1IR(2) 5210 U1IE U1EIR(2) 5240 U1EIE U1STAT 5250 (3) U1CON DS61156G-page 107 5260 U1ADDR 5270 U1BDTP1 5280 (3) U1FRML Legend: Note 1: 2: 3: 4: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 22/6 21/5 — — 20/4 31:16 — — — — — — — — — 15:0 — — — — — — — — IDIF 31:16 — — — — — — — — — 15:0 — — — — — — — — IDIE 31:16 — — — — —
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Virtual Address (BF88_#) Register Name 5290 U1FRMH(3) USB REGISTER MAP(1) (CONTINUED) 52A0 U1TOK © 2009-2011 Microchip Technology Inc.
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Virtual Address (BF88_#) Register Name 53B0 U1EP11 53C0 U1EP12 53D0 U1EP13 53E0 U1EP14 53F0 U1EP15 USB REGISTER MAP(1) (CONTINUED) Legend: Note 1: 2: 3: 4: 20/4 19/3 18/2 17/1 16/0 All Resets Bits Bit Range © 2009-2011 Microchip Technology Inc.
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Virtual Address (BF88_#) Register Name B000 C1CON C1CFG B020 C1INT B030 B050 B060 C1VEC C1TREC C1FSTAT C1RXOVF B070 C1TMR B080 C1RXM0 B090 C1RXM1 B0A0 © 2009-2011 Microchip Technology Inc.
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Virtual Address (BF88_#) B100 C1FLTCON4 B110 C1FLTCON5 B120 C1FLTCON6 B130 C1FLTCON7 B140 B340 CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED) C1RXFn (n = 0-31) C1FIFOBA 28/12 27/11 26/10 25/9 24
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Virtual Address (BF88_#) Register Name C000 C2CON C010 C2CFG C040 C050 C060 C070 C080 C0A0 C0B0 © 2009-2011 Microchip Technology Inc.
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Virtual Address (BF88_#) C100 C2FLTCON4 C110 C2FLTCON5 C120 C2FLTCON6 C130 C2FLTCON7 C140 C340 CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED) C2RXFn (n = 0-31) C2FIFOBA C2FIFOINTn (n = 0-31) 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000 15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL1
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Virtual Address (BF88_#) Register Name 9000 ETHCON1 9010 ETHCON2 9020 9030 9040 9050 9060 9070 9080 9090 90A0 ETHTXST ETHRXST ETHHT0 ETHHT1 ETHPMM0 ETHPMM1 ETHPMCS ETHPMO ETHRXFC © 2009-2011 Microchip Technology Inc.
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Virtual Address (BF88_#) Register Name 90E0 ETHSTAT ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — —
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PIC32MX5XX/6XX/7XX 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Program Memory” (DS61121) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX 6.0 RESETS Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Resets” (DS61118) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.
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PIC32MX5XX/6XX/7XX 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Interrupts” (DS61108) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
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PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION Interrupt Source(1) IRQ Vector Number Interrupt Bit Location Flag Enable Priority Sub-Priority Highest Natural Order Priority CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> INT0 – External Interrupt 0 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<
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PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Bit Location IRQ Vector Number Flag Enable Priority Sub-Priority PMP – Parallel Master Port 34 28 IFS1<2> IEC1<2> IPC7<4:2> IPC7<1:0> CMP1 – Comparator Interrupt 35 29 IFS1<3> IEC1<3> IPC7<12:10> IPC7<9:8> CMP2 – Comparator Interrupt 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16> U3E – UART2A Error SPI2E – SPI2 Fault I2C4B – I2C4 Bus Collision Event 37 31 IFS1<5> IEC1<5> IPC7<28:26> I
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PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Bit Location IRQ Vector Number Flag Enable Priority Sub-Priority IC4E – Input Capture 5 Error 65 21 IFS2<1> IEC2<1> IPC5<12:10> IPC5<9:8> PMPE – Parallel Master Port Error 66 28 IFS2<2> IEC2<2> IPC7<4:2> IPC7<1:0> U4E – UART4 Error 67 49 IFS2<3> IEC2<3> IPC12<12:10> IPC12<9:8> U4RX – UART4 Receiver 68 49 IFS2<4> IEC2<4> IPC12<12:10> IPC12<9:8> U4TX – UART4 Transmitter 69 49 IFS2<
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PIC32MX5XX/6XX/7XX 8.
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PIC32MX5XX/6XX/7XX PREFETCH CACHE Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Prefetch Cache” (DS61119) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
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PIC32MX5XX/6XX/7XX 10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. “Direct Memory Access (DMA) Controller” (DS61117) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX 11.0 USB ON-THE-GO (OTG) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. “USB OnThe-Go (OTG)” (DS61126) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX FIGURE 11-1: PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM USBEN FRC Oscillator 8 MHz Typical USB Suspend CPU Clock Not POSC Sleep TUN<5:0>(4) Primary Oscillator (POSC) Div x OSC1 UFIN(5) PLL UPLLEN(6) UPLLIDIV(6) USB Suspend OSC2 (PB Out)(1) Div 2 UFRCEN(3) To Clock Generator for Core and Peripherals Sleep or Idle USB Module SRP Charge Bus SRP Discharge USB Voltage Comparators 48 MHz USB Clock(7) Full Speed Pull-up D+(2) Registers and Control Interface Host Pull-down
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PIC32MX5XX/6XX/7XX 12.0 I/O PORTS General purpose I/O pins are the simplest of peripherals. They allow the PIC® MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin.
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PIC32MX5XX/6XX/7XX 12.1 Parallel I/O (PIO) Ports All port pins have three registers (TRIS, LAT and PORT) that are directly associated with their operation. TRIS is a Data Direction or Tri-State Control register that determines whether a digital pin is an input or an output. Setting a TRISx register bit = 1, configures the corresponding I/O pin as an input; setting a TRISx register bit = 0, configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a device Reset.
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PIC32MX5XX/6XX/7XX 13.0 TIMER1 This family of PIC32 devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Low-Power Secondary Oscillator (SOSC) for Real-Time Clock (RTC) applications. The following modes are supported: Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices.
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PIC32MX5XX/6XX/7XX 14.0 TIMER2/3, TIMER4/5 Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14.
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PIC32MX5XX/6XX/7XX FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1) Reset TMRy MS Half Word ADC Event Trigger(3) Equal Sync LS Half Word 32-bit Comparator PRy TyIF Event Flag TMRx PRx 0 1 TGATE (TxCON<7>) Q D TGATE (TxCON<7>) Q TCS (TxCON<1>) ON (TxCON<15>) TxCK(2) x1 Gate Sync PBCLK 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of ‘y’ in re
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PIC32MX5XX/6XX/7XX 15.0 INPUT CAPTURE 1. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. “Input Capture” (DS61122) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2. 3. 4.
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PIC32MX5XX/6XX/7XX 16.0 OUTPUT COMPARE The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the OCMP module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of operation. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices.
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PIC32MX5XX/6XX/7XX 17.0 SERIAL PERIPHERAL INTERFACE (SPI) The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters, etc. The PIC32 SPI module is compatible with Motorola® SPI and SIOP interfaces. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices.
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PIC32MX5XX/6XX/7XX 18.0 INTER-INTEGRATED CIRCUIT™ (I2C™) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “InterIntegrated Circuit™ (I2C™)” (DS61116) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX FIGURE 18-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read PBCLK DS61156G-page 146 © 2009-2011 Microchip Techno
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PIC32MX5XX/6XX/7XX 19.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS61107) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX Figure 19-2 and Figure 19-3 illustrate typical receive and transmit timing for the UART module.
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PIC32MX5XX/6XX/7XX 20.0 PARALLEL MASTER PORT (PMP) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Parallel Master Port (PMP)” (DS61128) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX 21.0 REAL-TIME CLOCK AND CALENDAR (RTCC) Following are some of the key features of this module: • • • • Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX 22.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC FRC Div 2 1 TAD ADCS<7:0> 0 8 TPB ADC Conversion Clock Multiplier 2, 4,..., 512 DS61156G-page 154 © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX 23.0 CONTROLLER AREA NETWORK (CAN) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 34. “Controller Area Network (CAN)” (DS61154) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX 24.0 ETHERNET CONTROLLER Following are some of the key features of this module: Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 35. “Ethernet Controller” (DS61155) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX Table 24-1, Table 24-2, Table 24-3 and Table 24-4 show four interfaces and the associated pins that can be used with the Ethernet Controller.
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PIC32MX5XX/6XX/7XX 25.0 COMPARATOR The Analog Comparator module contains two comparators that can be configured in a variety of ways. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Comparator” (DS61110) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX 26.0 COMPARATOR VOLTAGE REFERENCE (CVREF) The CVREF module is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 20.
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PIC32MX5XX/6XX/7XX 27.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “PowerSaving Features” (DS61130) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
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PIC32MX5XX/6XX/7XX The processor will exit, or ‘wake-up’, from Sleep on one of the following events: The processor will wake or exit from Idle mode on the following events: • On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority.
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PIC32MX5XX/6XX/7XX 28.0 Note: SPECIAL FEATURES This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Watchdog Timer and Power-up Timer” (DS61114), Section 24. “Configuration” (DS61124) and Section 33.
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PIC32MX5XX/6XX/7XX REGISTER 28-1: Bit Range 31:24 23:16 15:8 7:0 DEVCFG0: DEVICE CONFIGURATION WORD 0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P — — — CP — — — BWP R/P R/P R/P R/P r-1 r-1 r-1 r-1 — — — — R/P R/P R/P R/P PWP<3:0> PWP<7:4> r-1 r-1 r-1 r-1 — — — — R/P R/P r-1 r-1 r-1 r-1 R/P r-1 — — — — ICESEL — DEBUG<1:0> Legend: R = Rea
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PIC32MX5XX/6XX/7XX REGISTER 28-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) bit 11-4 Reserved: Write ‘1’ bit 3 ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit 1 = PGEC2/PGED2 pair is used 0 = PGEC1/PGED1 pair is used bit 2 Reserved: Write ‘1’ bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled) 11 = Debugger is disabled 10 = Debugger is enabled 01 = Reserved (same as ‘11’ setting) 00 = Reserved (same as ‘11’ setting) © 2009-20
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PIC32MX5XX/6XX/7XX REGISTER 28-2: Bit Range 31:24 23:16 15:8 7:0 DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — R/P R/P R/P R/P R/P R/P R/P R/P r-1 r-1 FWDTEN — — R/P R/P R/P FCKSM<1:0> WDTPS<4:0> R/P FPBDIV<1:0> r-1 R/P — OSCIOFNC R/P R/P r-1 R/P r-1 r-1 IESO — FSOSCEN — — POSCMOD<1:0> R/P R/P
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PIC32MX5XX/6XX/7XX REGISTER 28-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 bit 11 Reserved: Write ‘1’ bit 10 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output disabled 0 = CLKO output signal active on the OSCO pin; Primary Oscillator must be disabled or configured for the External Cloc
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PIC32MX5XX/6XX/7XX REGISTER 28-3: Bit Range 31:24 23:16 15:8 7:0 DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — R/P R/P R/P r-1 r-1 r-1 r-1 r-1 — — — — — R/P r-1 r-1 r-1 r-1 UPLLEN — — — — r-1 R/P-1 R/P R/P-1 — Legend: R = Readable bit U = Unimplemented bit FPLLMUL<2:0> W = Writable bit ‘1’ = Bit i
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PIC32MX5XX/6XX/7XX REGISTER 28-4: Bit Range 31:24 23:16 15:8 7:0 DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 R/P R/P FVBUSONIO FUSBIDIO Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 R/P R/P R/P — — — FCANIO(1) FETHIO(2) FMIIEN(2) R/P R/P R/P r-1 r-1 r-1 r-1 r-1 — — — — — R/P R/P R/P R/P R/P FSRSSEL<2:0> R/P R/P R/P R/P R/P R/P USERID<15:8> R/P R/P R/P R/P R/P USERID<7:0> Legen
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PIC32MX5XX/6XX/7XX REGISTER 28-5: Bit Range 31:24 23:16 15:8 7:0 DEVID: DEVICE AND REVISION ID REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R R R R R VER<3:0>(1) R R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R DEVID<27:24>(1) R R R R R R R R R R R R DEVID<23:16>(1) R R R R R DEVID<15:8>(1) R R R R R DEVID<7:0>(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit
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PIC32MX5XX/6XX/7XX 28.2 Watchdog Timer (WDT) This section describes the operation of the WDT and Power-up Timer of the PIC32MX5XX/6XX/7XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode.
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PIC32MX5XX/6XX/7XX 28.3 On-Chip Voltage Regulator 28.3.3 POWER-UP REQUIREMENTS All PIC32MX5XX/6XX/7XX devices’ core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX5XX/6XX/7XX family incorporate an on-chip regulator providing the required core logic voltage from VDD. The on-chip regulator is designed to meet the power-up requirements for the device.
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PIC32MX5XX/6XX/7XX 28.4 Programming and Diagnostics PIC32MX5XX/6XX/7XX devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them.
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PIC32MX5XX/6XX/7XX REGISTER 28-6: Bit Range 31:24 23:16 15:8 7:0 DDPCON: DEBUG DATA PORT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-1 R/W-0 U-0 R/W-0 — — — — JTAGEN TROEN — TDOEN Le
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PIC32MX5XX/6XX/7XX 29.0 INSTRUCTION SET The PIC32MX5XX/6XX/7XX family instruction set complies with the MIPS32 Release 2 instruction set architecture. The PIC32 device family does not support the following features: • Core extend instructions • Coprocessor 1 instructions • Coprocessor 2 instructions Note: Refer to “MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set” at www.mips.com for more information. © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX 30.
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PIC32MX5XX/6XX/7XX 30.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 30.
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PIC32MX5XX/6XX/7XX 30.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
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PIC32MX5XX/6XX/7XX 30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
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PIC32MX5XX/6XX/7XX 31.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
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PIC32MX5XX/6XX/7XX 31.1 DC Characteristics TABLE 31-1: OPERATING MIPS VS. VOLTAGE Max. Frequency VDD Range (in Volts) Temp. Range (in °C) PIC32MX5XX/6XX/7XX DC5 2.3-3.6V -40°C to +85°C 80 MHz DC5b 2.3-3.6V -40°C to +105°C 80 MHz Characteristic TABLE 31-2: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typical Max.
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PIC32MX5XX/6XX/7XX TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) DC CHARACTERISTICS Param. Typical(3) No. Max. Standard Operating Conditions: 2.3V to 3.
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PIC32MX5XX/6XX/7XX TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE): Core Off, Clock on Base Current(1) for PIC32MX575/675/695/775 Family Devices DC30 4.5 6.
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PIC32MX5XX/6XX/7XX TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Param. Typical(2) No. Max. Standard Operating Conditions: 2.3V to 3.
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PIC32MX5XX/6XX/7XX TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Param. Typical(2) No. Max. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp Units Conditions Module Differential Current(7) for PIC32MX534/564/664/764 Family Devices DC41c — 10 μA — 2.5V Watchdog Timer Current: ΔIWDT (Notes 3,6) DC41d 5 — μA — 3.
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PIC32MX5XX/6XX/7XX TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. VIL DI10 Characteristics Min. Typical(1 ) Max. Units Conditions Input Low Voltage I/O Pins: with TTL Buffer VSS — 0.15 VDD V with Schmitt Trigger Buffer VSS — 0.2 VDD V MCLR VSS — 0.
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PIC32MX5XX/6XX/7XX TABLE 31-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. VOL DO10 Characteristics Min. Typical Max. Units — — 0.4 V IOL = 7 mA, VDD = 3.6V — — 0.4 V IOL = 6 mA, VDD = 2.3V — — 0.4 V IOL = 3.5 mA, VDD = 3.6V — — 0.4 V IOL = 2.5 mA, VDD = 2.
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PIC32MX5XX/6XX/7XX TABLE 31-11: DC CHARACTERISTICS: PROGRAM MEMORY(3) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical(1) Max. Units Conditions — E/W — E/W See Note 4 Program Flash Memory D130 EP Cell Endurance 1000 — D130a EP Cell Endurance 20,000 — — D131 VPR VDD for Read 2.3 — 3.
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PIC32MX5XX/6XX/7XX TABLE 31-12: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp Required Flash Wait States SYSCLK Units Comments 0 Wait State 0 to 30 MHz — 1 Wait State 31 to 60 2 Wait States 61 to 80 TABLE 31-13: COMPARATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.
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PIC32MX5XX/6XX/7XX TABLE 31-14: VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. D310 Characteristics VRES Resolution Min. Typical Max. Units Comments VDD/24 — VDD/32 LSb — D311 VRAA Absolute Accuracy — — 1/2 LSb — D312 TSET Settling Time(1) — — 10 μs — D313 VIREF Internal Voltage Reference — 0.
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PIC32MX5XX/6XX/7XX 31.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX5XX/6XX/7XX AC characteristics and timing parameters.
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PIC32MX5XX/6XX/7XX TABLE 31-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. OS10 FOSC OS11 Min. Typical(1) Max.
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PIC32MX5XX/6XX/7XX TABLE 31-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max.
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PIC32MX5XX/6XX/7XX TABLE 31-20: INTERNAL RC ACCURACY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. No. Characteristics Min. Typical Max. Units Conditions -15 — +15 % — LPRC @ 31.25 kHz(1) F21 LPRC Note 1: Change of LPRC frequency as VDD changes.
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PIC32MX5XX/6XX/7XX FIGURE 31-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) CPU Starts Fetching Code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) Note 1: 2: SY10 (TOST) CPU Starts Fetching Code The power-up period will be
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PIC32MX5XX/6XX/7XX FIGURE 31-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code TOST (SY10) TABLE 31-22: RESETS TIMING Standard Operating Conditions: 2.3V to 3.
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PIC32MX5XX/6XX/7XX FIGURE 31-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 31-1 for load conditions. TABLE 31-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. No.
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PIC32MX5XX/6XX/7XX TABLE 31-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Max. Units Conditions TB10 TTXH TxCK Synchronous, with High Time prescaler [(12.
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PIC32MX5XX/6XX/7XX FIGURE 31-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM mode) OC10 OC11 Note: Refer to Figure 31-1 for load conditions. TABLE 31-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max.
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PIC32MX5XX/6XX/7XX FIGURE 31-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP31 SDIx LSb SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
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PIC32MX5XX/6XX/7XX FIGURE 31-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 LSb Bit 14 - - - - - -1 MSb SDOX SP30,SP31 SDIX Bit 14 - - - -1 MSb In SP40 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
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PIC32MX5XX/6XX/7XX FIGURE 31-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
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PIC32MX5XX/6XX/7XX FIGURE 31-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP40 SP51 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
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PIC32MX5XX/6XX/7XX TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max.
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PIC32MX5XX/6XX/7XX FIGURE 31-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 31-1 for load conditions. FIGURE 31-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 31-1 for load conditions. DS61156G-page 208 © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. IM10 Min.(1) Max.
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PIC32MX5XX/6XX/7XX FIGURE 31-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition Note: Refer to Figure 31-1 for load conditions. FIGURE 31-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 31-1 for load conditions. DS61156G-page 210 © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. No.
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PIC32MX5XX/6XX/7XX FIGURE 31-18: CiTx Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CiRx Pin (input) CA20 TABLE 31-34: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param No.
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PIC32MX5XX/6XX/7XX TABLE 31-35: ETHERNET MODULE SPECIFICATIONS AC CHARACTERISTICS Param. No. Characteristic Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp Min. Typical Max.
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PIC32MX5XX/6XX/7XX TABLE 31-36: ADC MODULE SPECIFICATIONS(5) AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp Min. Typical Max. Units Conditions Greater of VDD – 0.3 or 2.5 — Lesser of VDD + 0.3 or 3.6 V VSS — VSS + 0.3 V AVSS + 2.0 — AVDD V (Note 1) 2.5 — 3.
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PIC32MX5XX/6XX/7XX TABLE 31-36: ADC MODULE SPECIFICATIONS(5) (CONTINUED) AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp Min. Typical Max. Units Conditions ADC Accuracy – Measurements with Internal VREF+/VREF- AD20d Nr Resolution AD21d INL Integral Nonlinearity > -1 — <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.
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PIC32MX5XX/6XX/7XX TABLE 31-37: 10-BIT ADC CONVERSION RATE PARAMETERS(2) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp ADC Speed TAD Minimum 1 Msps to 400 ksps(1) 65 ns Sampling RS Time Maximum Mininum 132 ns 500Ω ADC Channels Configuration VDD 3.0V to 3.6V VREF- VREF+ ANx Up to 400 ksps 200 ns 200 ns 5.0 kΩ CHX SHA ADC 2.5V to 3.
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PIC32MX5XX/6XX/7XX TABLE 31-38: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical(1) Max.
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PIC32MX5XX/6XX/7XX FIGURE 31-19: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 17. “10-bit A/D Converter” (DS61104) of the “PIC32 Family Reference Manual”.
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PIC32MX5XX/6XX/7XX FIGURE 31-20: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp eoc TSAMP AD55 TSAMP AD55 TCONV CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
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PIC32MX5XX/6XX/7XX FIGURE 31-21: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2 TABLE 31-39: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical Max.
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PIC32MX5XX/6XX/7XX FIGURE 31-22: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 Address PMA<13:18> PM6 PMD<7:0> Data Data Address<7:0> Address<7:0> PM2 PM7 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 31-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No.
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PIC32MX5XX/6XX/7XX FIGURE 31-23: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock Address PMA<13:18> PM2 + PM3 Address<7:0> PMD<7:0> Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 31-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No.
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PIC32MX5XX/6XX/7XX TABLE 31-42: OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) USB313 VUSB USB Voltage Min. Typical Max. Units 3.0 — 3.6 V Conditions Voltage on VUSB must be in this range for proper USB operation USB315 VILUSB Input Low Voltage for USB Buffer — — 0.
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PIC32MX5XX/6XX/7XX FIGURE 31-24: EJTAG TIMING CHARACTERISTICS TTCKeye TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TRST* TTRST*low TTDOout TTDOzstate Defined Trf Undefined TABLE 31-43: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-Temp AC CHARACTERISTICS Param. No. Symbol Description(1) Min. Max.
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PIC32MX5XX/6XX/7XX 32.0 PACKAGING INFORMATION 32.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) PIC32MX575F 512H-80I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 0510017 100-Lead TQFP (14x14x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
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PIC32MX5XX/6XX/7XX 32.1 Package Marking Information (Continued) 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 121-Lead XBGA (10x10x1.1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS61156G-page 226 Example PIC32MX575F 512H-80I/MR e3 0510017 Example PIC32MX575F 512H-80I/BG e3 0510017 © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX 32.2 Package Details The following sections give the technical details of the packages.
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PIC32MX5XX/6XX/7XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS61156G-page 228 © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 3) ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS61156G-page 230 © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV A2 L1 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± )RRW
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PIC32MX5XX/6XX/7XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS61156G-page 232 © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61156G-page 234 © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61156G-page 236 © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61156G-page 238 © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX APPENDIX A: MIGRATING FROM PIC32MX3XX/4XX TO PIC32MX5XX/6XX/7XX DEVICES This appendix provides an overview of considerations for migrating from PIC32MX3XX/4XX devices to the PIC32MX5XX/6XX/7XX family of devices. The code developed for the PIC32MX3XX/4XX devices can be ported to the PIC32MX5XX/6XX/7XX devices after making the appropriate changes outlined below. A.
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PIC32MX5XX/6XX/7XX APPENDIX B: REVISION HISTORY Revision B (November 2009) The revision includes the following global update: Revision A (August 2009) This is the initial released version of this document. • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits. Other major changes are referenced by their respective chapter/section in Table B-1.
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PIC32MX5XX/6XX/7XX TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Section Name 4.0 “Memory Organization” Update Description Updated all register tables to include the Virtual Address and All Resets columns. Updated the title of Figure 4-4 to include the PIC32MX575F256L device. Updated the title of Figure 4-6 to include the PIC32MX695F512L and PIC32MX695F512H devices. Also changed PIC32MX795F512L to PIC32MX795F512H. Updated the title of Table 4-3 to include the PIC32MX695F512H device.
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PIC32MX5XX/6XX/7XX Revision C (February 2010) The revision includes the following updates, as described in Table B-2: TABLE B-2: MAJOR SECTION UPDATES Section Name “High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers” Update Description Added the following devices: • • • • • • PIC32MX675F256H PIC32MX775F256H PIC32MX775F512H PIC32MX675F256L PIC32MX775F256L PIC32MX775F512L Added the following pins: • • • • 1.
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PIC32MX5XX/6XX/7XX Revision D (May 2010) The revision includes the following updates, as described in Table B-3: TABLE B-3: MAJOR SECTION UPDATES Section Name “High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers” Update Description Updated the initial Flash memory range to 64K. Updated the initial SRAM memory range to 16K. Added the following devices (see Table 1, Table 2, Table 3 and the Pin Diagrams): • • • • • • • • • • • • 4.
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PIC32MX5XX/6XX/7XX TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Section Name 4.
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PIC32MX5XX/6XX/7XX TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Section Name 31.0 “Electrical Characteristics” Update Description Updated the Typical and Maximum DC Characteristics: Operating Current (IDD) in Table 31-5. Updated the Typical and Maximum DC Characteristics: Idle Current (IIDLE) in Table 31-6. Updated the Typical and Maximum DC Characteristics: Power-Down Current (IPD) in Table 31-7. Added DC Characteristics: Program Memory parameters D130a and D132a in Table 31-11.
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PIC32MX5XX/6XX/7XX Revision E (July 2010) Revision F (December 2010) Minor corrections were incorporated throughout the document.
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PIC32MX5XX/6XX/7XX TABLE B-4: SECTION UPDATES (CONTINUED) Section Name 4.0 “Memory Organization” (Continued) © 2009-2011 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX TABLE B-4: SECTION UPDATES (CONTINUED) Section Name 7.0 “Interrupt Controller” 8.0 “Oscillator Configuration” 16.0 “Output Compare” 24.0 “Ethernet Controller” 26.0 “Comparator Voltage Reference (CVREF)” 28.0 “Special Features” 31.
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PIC32MX5XX/6XX/7XX Revision G (May 2011) The revision includes the following global update: • All references to VDDCORE/VCAP have been changed to: VCORE/VCAP • Added references to the new V-Temp temperature range: -40ºC to +105ºC TABLE B-5: This revision also includes minor typographical and formatting changes throughout the data sheet text. Major updates are referenced by their respective section in the following table.
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PIC32MX5XX/6XX/7XX INDEX A D AC Characteristics ............................................................ 194 10-bit Conversion Rate Parameters.......................... 216 ADC Specifications ................................................... 214 Analog-to-Digital Conversion Requirements............. 217 EJTAG Timing Requirements ................................... 224 Ethernet .................................................................... 213 Internal FRC Accuracy..............................
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PIC32MX5XX/6XX/7XX Details ....................................................................... 227 Marking ..................................................................... 225 Parallel Master Port (PMP) ............................................... 149 PIC32 Family USB Interface Diagram............................... 132 Pinout I/O Descriptions (table) ............................................ 32 Power-on Reset (POR) and On-Chip Voltage Regulator ................................
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PIC32MX5XX/6XX/7XX THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC32MX5XX/6XX/7XX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC32MX5XX/6XX/7XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 5XX F 512 H T - 80 I / PT - XXX Example: PIC32MX575F256H-80I/PT: General purpose PIC32, 32-bit RISC MCU, 256 KB program memory, 64-pin, Industrial temperature, TQFP package.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.