Information

Pinouts and pin description STM32F405xx, STM32F407xx
48/185 DocID022152 Rev 4
17 H9 26 37 R2 47 PA3 I/O FT
(4)
USART2_RX/TIM5_CH4 /
TIM9_CH2 / TIM2_CH4 /
OTG_HS_ULPI_D0 /
ETH_MII_COL/
EVENTOUT
ADC123_IN3
18 E5 27 38 - - V
SS
S
D9 L4 48 BYPASS_REG I FT
19 E4 28 39 K4 49 V
DD
S
20 J9 29 40 N4 50 PA4 I/O TTa
(4)
SPI1_NSS / SPI3_NSS /
USART2_CK /
DCMI_HSYNC /
OTG_HS_SOF/ I2S3_WS/
EVENTOUT
ADC12_IN4
/DAC_OUT1
21 G8 30 41 P4 51 PA5 I/O TTa
(4)
SPI1_SCK/
OTG_HS_ULPI_CK /
TIM2_CH1_ETR/
TIM8_CH1N/ EVENTOUT
ADC12_IN5/DAC_OU
T2
22 H8 31 42 P3 52 PA6 I/O FT
(4)
SPI1_MISO /
TIM8_BKIN/TIM13_CH1 /
DCMI_PIXCLK /
TIM3_CH1 / TIM1_BKIN/
EVENTOUT
ADC12_IN6
23 J8 32 43 R3 53 PA7 I/O FT
(4)
SPI1_MOSI/ TIM8_CH1N
/ TIM14_CH1/TIM3_CH2/
ETH_MII_RX_DV /
TIM1_CH1N /
ETH_RMII_CRS_DV/
EVENTOUT
ADC12_IN7
24 - 33 44 N5 54 PC4 I/O FT
(4)
ETH_RMII_RX_D0 /
ETH_MII_RX_D0/
EVENTOUT
ADC12_IN14
25 - 34 45 P5 55 PC5 I/O FT
(4)
ETH_RMII_RX_D1 /
ETH_MII_RX_D1/
EVENTOUT
ADC12_IN15
26 G7 35 46 R5 56 PB0 I/O FT
(4)
TIM3_CH3 / TIM8_CH2N/
OTG_HS_ULPI_D1/
ETH_MII_RXD2 /
TIM1_CH2N/ EVENTOUT
ADC12_IN8
Table 7. STM32F40x pin and ball definitions (continued)
Pin number
Pin name
(function after
reset)
(1)
Pin type
I / O structure
Notes
Alternate functions Additional functions
LQFP64
WLCSP90
LQFP100 LQFP144
UFBGA176
LQFP176