Information

Revision history STM32F405xx, STM32F407xx
180/185 DocID022152 Rev 4
31-May-2012
3
(continued)
Removed f
HSE_ext
typical value in Table 29: High-speed external user
clock characteristics. Updated Table 31: HSE 4-26 MHz oscillator
characteristics and Table 32: LSE oscillator characteristics (fLSE =
32.768 kHz).
Added f
PLL48_OUT
maximum value in Table 35: Main PLL
characteristics.
Modified equation 1 and 2 in Section 5.3.11: PLL spread spectrum
clock generation (SSCG) characteristics.
Updated Table 38: Flash memory characteristics, Table 39: Flash
memory programming, and Table 40: Flash memory programming with
VPP.
Updated Section : Output driving current.
Table 53: I2C characteristics: Note 4 updated and applied to t
h(SDA)
in
Fast mode, and removed note 4 related to t
h(SDA)
minimum value.
Updated Table 67: ADC characteristics. Updated note concerning ADC
accuracy vs. negative injection current below Table 68: ADC accuracy
at fADC = 30 MHz.
Added WLCSP90 thermal resistance in Table 96: Package thermal
characteristics.
Updated Table 90: WLCSP90 - 0.400 mm pitch wafer level chip size
package mechanical data.
Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array
10 × 10 × 0.6 mm, package outline and Table 94: UFBGA176+25 -
ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data.
Added Figure 85: LQFP176 recommended footprint.
Removed 256 and 768 Kbyte Flash memory density from Table 97:
Ordering information scheme.
Table 98. Document revision history (continued)
Date Revision Changes