Information

Electrical characteristics STM32F405xx, STM32F407xx
146/185 DocID022152 Rev 4
Figure 62. Synchronous non-multiplexed PSRAM write timings
t
d(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x= 0…2) 0 - ns
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low - 2 ns
t
d(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high 3 - ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns
t
d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x=16…25) 2 - ns
t
d(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low - 0.5 ns
t
d(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high 1.5 - ns
t
su(DV-CLKH)
FSMC_D[15:0] valid data before FSMC_CLK high 6 - ns
t
h(CLKH-DV)
FSMC_D[15:0] valid data after FSMC_CLK high 3 - ns
t
su(NWAIT-CLKH)
FSMC_NWAIT valid before FSMC_CLK high 4 - ns
t
h(CLKH-NWAIT)
FSMC_NWAIT valid after FSMC_CLK high 0 - ns
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Table 81. Synchronous non-multiplexed NOR/PSRAM read timings
(1)(2)
(continued)
FSMC_CLK
FSMC_NEx
FSMC_A[25:0]
FSMC_NWE
FSMC_D[15:0]
D1 D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 0
BUSTURN = 0
t
d(CLKL-NExL)
t
d(CLKL-NExH)
t
d(CLKL-AV)
t
d(CLKL-AIV)
t
d(CLKL-NWEH)
t
d(CLKL-NWEL)
t
d(CLKL-Data)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
ai14993g
FSMC_NADV
t
d(CLKL-NADVL)
t
d(CLKL-NADVH)
t
d(CLKL-Data)
FSMC_NBL
t
d(CLKL-NBLH)