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DocID022152 Rev 4 145/185
STM32F405xx, STM32F407xx Electrical characteristics
Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings
t
d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns
t
d(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low - 0.5 ns
t
d(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high 0 - ns
t
d(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns
t
d(CLKL-DATA)
FSMC_A/D[15:0] valid data after FSMC_CLK low - 3 ns
t
d(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high 0 - ns
t
su(NWAIT-CLKH)
FSMC_NWAIT valid before FSMC_CLK high 4 - ns
t
h(CLKH-NWAIT)
FSMC_NWAIT valid after FSMC_CLK high 0 - ns
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Table 81. Synchronous non-multiplexed NOR/PSRAM read timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 2T
HCLK
–0.5 - ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x=0..2) - 0.5 ns
Table 80. Synchronous multiplexed PSRAM write timings
(1)(2)
FSMC_CLK
FSMC_NEx
FSMC_A[25:0]
FSMC_NOE
FSMC_D[15:0]
D1 D2
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 0
BUSTURN = 0
t
d(CLKL-NExL)
t
d(CLKL-NExH)
t
d(CLKL-AV)
t
d(CLKL-AIV)
t
d(CLKL-NOEL)
t
d(CLKL-NOEH)
t
su(DV-CLKH)
t
h(CLKH-DV)
t
su(DV-CLKH)
t
h(CLKH-DV)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
ai14894f
FSMC_NADV
t
d(CLKL-NADVL)
t
d(CLKL-NADVH)