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Electrical characteristics STM32F405xx, STM32F407xx
144/185 DocID022152 Rev 4
Figure 60. Synchronous multiplexed PSRAM write timings
t
h(CLKH-ADV)
FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns
t
su(NWAIT-CLKH)
FSMC_NWAIT valid before FSMC_CLK high 4 - ns
t
h(CLKH-NWAIT)
FSMC_NWAIT valid after FSMC_CLK high 0 - ns
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Table 80. Synchronous multiplexed PSRAM write timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 2T
HCLK
-ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns
t
d(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low - 0 ns
t
d(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high 0 - ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns
Table 79. Synchronous multiplexed NOR/PSRAM read timings
(1)(2)
(continued)
FSMC_CLK
FSMC_NEx
FSMC_NADV
FSMC_A[25:16]
FSMC_NWE
FSMC_AD[15:0] AD[15:0] D1 D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 0
BUSTURN = 0
t
d(CLKL-NExL)
t
d(CLKL-NExH)
t
d(CLKL-NADVL)
t
d(CLKL-AV)
t
d(CLKL-NADVH)
t
d(CLKL-AIV)
t
d(CLKL-NWEH)
t
d(CLKL-NWEL)
t
d(CLKL-NBLH)
t
d(CLKL-ADV)
t
d(CLKL-ADIV)
t
d(CLKL-Data)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
ai14992g
t
d(CLKL-Data)
FSMC_NBL