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DocID022152 Rev 4 141/185
STM32F405xx, STM32F407xx Electrical characteristics
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms
t
v(NADV_NE)
FSMC_NEx low to FSMC_NADV low 1 2 ns
t
w(NADV)
FSMC_NADV low time T
HCLK
– 2 T
HCLK
+1 ns
t
h(AD_NADV)
FSMC_AD(adress) valid hold time after
FSMC_NADV high)
T
HCLK
-ns
t
h(A_NOE)
Address hold time after FSMC_NOE high T
HCLK
–1 - ns
t
h(BL_NOE)
FSMC_BL time after FSMC_NOE high 0 - ns
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid - 2 ns
t
su(Data_NE)
Data to FSMC_NEx high setup time T
HCLK
+4 - ns
t
su(Data_NOE)
Data to FSMC_NOE high setup time T
HCLK
+4 - ns
t
h(Data_NE)
Data hold time after FSMC_NEx high 0 - ns
t
h(Data_NOE)
Data hold time after FSMC_NOE high 0 - ns
1. C
L
= 30 pF.
2. Based on characterization, not tested in production.
Table 78. Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 4T
HCLK
–0.5 4T
HCLK
+3 ns
t
v(NWE_NE)
FSMC_NEx low to FSMC_NWE low T
HCLK
–0.5 T
HCLK
-0.5 ns
t
w(NWE)
FSMC_NWE low tim e 2T
HCLK
–0.5 2T
HCLK
+3 ns
Table 77. Asynchronous multiplexed PSRAM/NOR read timings
(1)(2)
(continued)
NBL
Data
FSMC_NEx
FSMC_NBL[1:0]
FSMC_
AD[15:0]
t
v(BL_NE)
t
h(Data_NWE)
FSMC_NOE
Address
FSMC_A[25:16]
t
v(A_NE)
t
w(NWE)
FSMC_NWE
t
v(NWE_NE)
t
h(NE_NWE)
t
h(A_NWE)
t
h(BL_NWE)
t
v(A_NE)
t
w(NE)
ai14891B
Address
FSMC_NADV
t
v(NADV_NE)
t
w(NADV)
t
v(Data_NADV)
t
h(AD_NADV)