Information
Electrical characteristics STM32F405xx, STM32F407xx
136/185 DocID022152 Rev 4
DAC_OUT
min
(2)
Lower DAC_OUT voltage
with buffer OFF
-0.5 - mV
It gives the maximum output
excursion of the DAC.
DAC_OUT
max
(2)
Higher DAC_OUT voltage
with buffer OFF
--V
REF+
– 1LSB V
I
VREF+
(4)
DAC DC V
REF
current
consumption in quiescent
mode (Standby mode)
- 170 240
µA
With no load, worst code (0x800)
at V
REF+
= 3.6 V in terms of DC
consumption on the inputs
-50 75
With no load, worst code (0xF1C)
at V
REF+
= 3.6 V in terms of DC
consumption on the inputs
I
DDA
(4)
DAC DC VDDA current
consumption in quiescent
mode
(3)
- 280 380 µA
With no load, middle code (0x800)
on the inputs
- 475 625 µA
With no load, worst code (0xF1C)
at V
REF+
= 3.6 V in terms of DC
consumption on the inputs
DNL
(4)
Differential non linearity
Difference between two
consecutive code-1LSB)
-- ±0.5 LSB
Given for the DAC in 10-bit
configuration.
-- ±2 LSB
Given for the DAC in 12-bit
configuration.
INL
(4)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
-- ±1 LSB
Given for the DAC in 10-bit
configuration.
-- ±4 LSB
Given for the DAC in 12-bit
configuration.
Offset
(4)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value
= V
REF+
/2)
-- ±10 mV
Given for the DAC in 12-bit
configuration
-- ±3 LSB
Given for the DAC in 10-bit at
V
REF+
= 3.6 V
-- ±12 LSB
Given for the DAC in 12-bit at
V
REF+
= 3.6 V
Gain
error
(4)
Gain error - - ±0.5 %
Given for the DAC in 12-bit
configuration
t
SETTLING
(4)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±4LSB
-3 6 µs
C
LOAD
≤ 50 pF,
R
LOAD
≥ 5 kΩ
THD
(4)
Total Harmonic Distortion
Buffer ON
-- - dB
C
LOAD
≤ 50 pF,
R
LOAD
≥ 5 kΩ
Table 74. DAC characteristics (continued)
Symbol Parameter Min Typ Max Unit Comments