Information

Electrical characteristics STM32F405xx, STM32F407xx
132/185 DocID022152 Rev 4
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 51. Typical connection diagram using the ADC
1. Refer to Table 67 for the values of R
AIN
, R
ADC
and C
ADC
.
2. C
parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high C
parasitic
value downgrades conversion accuracy. To remedy this,
f
ADC
should be reduced.
ai17534
STM32F
V
DD
AINx
I
L
±1 µA
0.6 V
V
T
R
AIN
(1)
C
parasitic
V
AIN
0.6 V
V
T
R
ADC
(1)
C
ADC
(1)
12-bit
converter
Sample and hold ADC
converter