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STM32F405xx, STM32F407xx Electrical characteristics
USB HS characteristics
Unless otherwise specified, the parameters given in Table 62 for ULPI are derived from
tests performed under the ambient temperature, f
HCLK
frequency summarized in Table 61
and V
DD
supply voltage conditions summarized in Table 60, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5V
DD
.
Refer to Section Section 5.3.16: I/O port characteristics for more details on the
input/outputcharacteristics.
Table 59. USB OTG FS electrical characteristics
(1)
1. Guaranteed by design, not tested in production.
Driver characteristics
Symbol Parameter Conditions Min Max Unit
t
r
Rise time
(2)
2.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
C
L
= 50 pF 420ns
t
f
Fall time
(2)
C
L
= 50 pF 4 20 ns
t
rfm
Rise/ fall time matching t
r
/t
f
90 110 %
V
CRS
Output signal crossover voltage 1.3 2.0 V
Table 60. USB HS DC electrical characteristics
Symbol Parameter Min.
(1)
1. All the voltages are measured from the local ground potential.
Max.
(1)
Unit
Input level V
DD
USB OTG HS operating voltage 2.7 3.6 V
Table 61. USB HS clock timing parameters
(1)
Parameter Symbol Min Nominal Max Unit
f
HCLK
value to guarantee proper operation of
USB HS interface
30 MHz
Frequency (first transition) 8-bit ±10% F
START_8BIT
54 60 66 MHz
Frequency (steady state) ±500 ppm F
STEADY
59.97 60 60.03 MHz
Duty cycle (first transition) 8-bit ±10% D
START_8BIT
40 50 60 %
Duty cycle (steady state) ±500 ppm D
STEADY
49.975 50 50.025 %
Time to reach the steady state frequency and
duty cycle after the first transition
T
STEADY
--1.4ms
Clock startup time after the
de-assertion of SuspendM
Peripheral T
START_DEV
--5.6
ms
Host T
START_HOST
---
PHY preparation time after the first transition
of the input clock
T
PREP
---µs