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STM32F405xx, STM32F407xx Electrical characteristics
t
w(SCKH)
SCK high and low time
Master mode, SPI presc = 2,
2.7V < V
DD
< 3.6V
T
PCLK
-0.5 T
PCLK
T
PCLK
+0.5
ns
t
w(SCKL)
Master mode, SPI presc = 2,
1.7V < V
DD
< 3.6V
T
PCLK
-2 T
PCLK
T
PCLK
+2
t
su(NSS)
NSS setup time Slave mode, SPI presc = 2 4 x T
PCLK
--
t
h(NSS)
NSS hold time Slave mode, SPI presc = 2 2 x T
PCLK
t
su(MI)
Data input setup time
Master mode 6.5 - -
t
su(SI)
Slave mode 2.5 - -
t
h(MI)
Data input hold time
Master mode 2.5 - -
t
h(SI)
Slave mode 4 - -
t
a(SO)
(2)
Data output access time Slave mode, SPI presc = 2 0 - 4 x T
PCLK
t
dis(SO)
(3)
Data output disable time
Slave mode, SPI1,
2.7V < V
DD
< 3.6V
0-7.5
Slave mode, SPI1/2/3
1.7V < V
DD
< 3.6V
0-16.5
t
v(SO)
t
h(SO)
Data output valid/hold time
Slave mode (after enable edge),
SPI1, 2.7V < V
DD
< 3.6V
-1113
Slave mode (after enable edge),
SPI2/3, 2.7V < V
DD
< 3.6V
-1216.5
Slave mode (after enable edge),
SPI1, 1.7V < V
DD
< 3.6V
- 15.5 19
Slave mode (after enable edge),
SPI2/3, 1.7V < V
DD
< 3.6V
-1820.5
t
v(MO)
Data output valid time
Master mode (after enable edge),
SPI1 , 2.7V < V
DD
< 3.6V
--2.5
Master mode (after enable edge),
SPI1/2/3 , 1.7V < V
DD
< 3.6V
--4.5
t
h(MO)
Data output hold time Master mode (after enable edge) 0 - -
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
Table 55. SPI dynamic characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit