Information

Electrical characteristics STM32F405xx, STM32F407xx
114/185 DocID022152 Rev 4
Figure 38. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 50. Otherwise the reset is not taken into account by the device.
5.3.18 TIM timer characteristics
The parameters given in Table 51 and Table 52 are guaranteed by design.
Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 50. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL(NRST)
(1)
1. Guaranteed by design, not tested in production.
NRST Input low level voltage TTL ports
2.7 V ≤ V
DD
≤ 3.6 V
--0.8
V
V
IH(NRST)
(1)
NRST Input high level voltage 2 - -
V
IL(NRST)
(1)
NRST Input low level voltage CMOS ports
1.8 V ≤ V
DD
≤ 3.6 V
-0.3V
DD
V
IH(NRST)
(1)
NRST Input high level voltage 0.7V
DD
-
V
hys(NRST)
NRST Schmitt trigger voltage
hysteresis
-200 - mV
R
PU
Weak pull-up equivalent resistor
(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum
(~10% order).
V
IN
= V
SS
30 40 50 kΩ
V
F(NRST)
(1)
NRST Input filtered pulse - - 100 ns
V
NF(NRST)
(1)
NRST Input not filtered pulse V
DD
> 2.7 V 300 - - ns
T
NRST_OUT
Generated reset pulse duration
Internal
Reset source
20 - - µs
ai14132c
STM32Fxxx
R
PU
NRST
(2)
V
DD
Filter
Internal Reset
0.1 μF
External
reset circuit
(1)