Information

Electrical characteristics STM32F405xx, STM32F407xx
110/185 DocID022152 Rev 4
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters.
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed V
OL
/V
OH
) except PC13, PC14 and PC15 which can
sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the
speed should not exceed 2 MHz with a maximum load of 30 pF.
Table 47. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL
Input low level voltage
TTL ports
2.7 V
≤ V
DD
≤ 3.6 V
--0.8
V
V
IH
(1)
Input high level voltage 2.0 - -
V
IL
Input low level voltage
CMOS ports
1.8 V
≤ V
DD
≤ 3.6 V
- - 0.3V
DD
V
IH
(1)
Input high level voltage 0.7V
DD
--
--
V
hys
I/O Schmitt trigger voltage hysteresis
(2)
-200-
mV
IO FT Schmitt trigger voltage
hysteresis
(2)
5% V
DD
(3)
--
I
lkg
I/O input leakage current
(4)
V
SS
≤ V
IN
≤ V
DD
--±1
µA
I/O FT input leakage current
(4)
V
IN
= 5V - - 3
R
PU
Weak pull-up equivalent
resistor
(5)
All pins
except for
PA10 and
PB12
V
IN
= V
SS
30 40 50
kΩ
PA10 and
PB12
81115
R
PD
Weak pull-down
equivalent resistor
All pins
except for
PA10 and
PB12
V
IN
= V
DD
30 40 50
PA10 and
PB12
81115
C
IO
(6)
I/O pin capacitance 5 pF
1. Tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution
to the series resistance is minimum (~10% order).
6. Guaranteed by design, not tested in production.