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This is information on a product in full production.

June 2013 DocID022152 Rev 4 1/185

STM32F405xx

STM32F407xx

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB

OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

Datasheet - production data

Features

• Core: ARM 32-bit Cortex™-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Flash memory, frequency up to 168 MHz,

memory protection unit, 210 DMIPS/

1.25 DMIPS/MHz (Dhrystone 2.1), and DSP

instructions

• Memories

– Up to 1 Mbyte of Flash memory

– Up to 192+4 Kbytes of SRAM including 64-

Kbyte of CCM (core coupled memory) data

RAM

– Flexible static memory controller

supporting Compact Flash, SRAM,

PSRAM, NOR and NAND memories

• LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– 1.8 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC (1%

accuracy)

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC, 20×32 bit backup

registers + optional 4 KB backup SRAM

• 3×12-bit, 2.4 MSPS A/D converters: up to 24

channels and 7.2 MSPS in triple interleaved

mode

• 2×12-bit D/A converters

• General-purpose DMA: 16-stream DMA

controller with FIFOs and burst support

• Up to 17 timers: up to twelve 16-bit and two 32-

bit timers up to 168 MHz, each with up to 4

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input

• Debug mode

– Serial wire debug (SWD) & JTAG

interfaces

– Cortex-M4 Embedded Trace Macrocell™

• Up to 140 I/O ports with interrupt capability

– Up to 136 fast I/Os up to 84 MHz

– Up to 138 5 V-tolerant I/Os

• Up to 15 communication interfaces

– Up to 3 × I

C interfaces (SMBus/PMBus)

– Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO

7816 interface, LIN, IrDA, modem control)

– Up to 3 SPIs (42 Mbits/s), 2 with muxed

full-duplex I

S to achieve audio class

accuracy via internal audio PLL or external

clock

– 2 × CAN interfaces (2.0B Active)

– SDIO interface

• Advanced connectivity

– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY

– USB 2.0 high-speed/full-speed

device/host/OTG controller with dedicated

DMA, on-chip full-speed PHY and ULPI

– 10/100 Ethernet MAC with dedicated DMA:

supports IEEE 1588v2 hardware, MII/RMII

• 8- to 14-bit parallel camera interface up to

54 Mbytes/s

• True random number generator

• CRC calculation unit

• 96-bit unique ID

• RTC: subsecond accuracy, hardware calendar

LQFP64 (10 × 10 mm)

LQFP100 (14 × 14 mm)

LQFP144 (20 × 20 mm)

FBGA

UFBGA176

(10 × 10 mm)

LQFP176 (24 × 24 mm)

WLCSP90

Table 1. Device summary

Reference Part number

STM32F405xx

STM32F405RG, STM32F405VG, STM32F405ZG,

STM32F405OG, STM32F405OE

STM32F407xx

STM32F407VG, STM32F407IG, STM32F407ZG,

STM32F407VE, STM32F407ZE, STM32F407IE

www.st.com

Summary of content (185 pages)

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STM32F405xx STM32F407xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm.
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Contents STM32F405xx, STM32F407xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/185 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.
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STM32F405xx, STM32F407xx Contents 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 36 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 36 2.2.32 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . .
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Contents 6 7 STM32F405xx, STM32F407xx 5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 108 5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.16 I/O port characteristics . . . . . . . . . .
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STM32F405xx, STM32F407xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46.
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List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95.
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STM32F405xx, STM32F407xx Table 96. Table 97. Table 98. List of tables Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures STM32F405xx, STM32F407xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39.
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STM32F405xx, STM32F407xx Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83.
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List of figures Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. 10/185 STM32F405xx, STM32F407xx USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 172 USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F405xx, STM32F407xx 1 Introduction Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com.
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Description 2 STM32F405xx, STM32F407xx Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM® Cortex™-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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Table 2.
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Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix 3/2 (full duplex)(2) SPI / I2S I2C 3 USART/ UART 4/2 Communi USB cation OTG FS interfaces USB OTG HS Yes Yes CAN 2 SDIO Yes DocID022152 Rev 4 Camera interface GPIOs 12-bit ADC Number of channels No 51 72 Yes 82 114 72 82 114 140 13 16 24 24 LQFP144 UFBGA176 LQFP176 3 16 13 16 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 168 MHz 1.8 to 3.
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STM32F405xx, STM32F407xx 2.1 Description Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pinto-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family.
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Description STM32F405xx, STM32F407xx Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package 76 75 73 VSS 51 50 49 VSS VSS 100 99 (VSS) 19 26 20 1 0Ω Ω resistor or soldering bridge present for the STM32F10xxx configuration, not present in the STM32F4xx configuration 25 VSS VDD V SS VSS for STM32F10xx VDD for STM32F4xx Two 0 Ω resistors connected to: VDD VSS - VSS for the STM32F10xx - VSS for the STM32F4xx - VSS, VDD or NC for the STM32F2xx ai18488c Figure 3.
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STM32F405xx, STM32F407xx Description Figure 4.
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Description 2.2 STM32F405xx, STM32F407xx Device overview Figure 5.
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STM32F405xx, STM32F407xx 2.2.1 Description ARM® Cortex™-M4F core with embedded Flash and SRAM The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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Description 2.2.5 STM32F405xx, STM32F407xx CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity.
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STM32F405xx, STM32F407xx Description Figure 6. Multi-AHB matrix S1 S2 S4 S5 USB_HS_M MAC USB OTG Ethernet HS ETHERNET_M DMA_P2 DMA_MEM2 DMA_PI DMA_MEM1 S3 GP DMA2 S6 S7 M0 ICODE M1 DCODE ACCEL S0 GP DMA1 S-bus I-bus D-bus ARM Cortex-M4 64-Kbyte CCM data RAM Flash memory M2 SRAM1 112 Kbyte M3 SRAM2 16 Kbyte AHB1 peripherals AHB2 peripherals M4 M5 M6 APB1 APB2 FSMC Static MemCtl Bus matrix-S ai18490c 2.2.
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Description 2.2.9 STM32F405xx, STM32F407xx Flexible static memory controller (FSMC) The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: • Write FIFO • Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz. LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers.
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STM32F405xx, STM32F407xx Description clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz.
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Description STM32F405xx, STM32F407xx The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
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STM32F405xx, STM32F407xx Description Figure 8. PDR_ON and NRST control with internal reset OFF V DD PDR = 1.7 V or 1.8 V (1) time Reset by other source than power supply supervisor NRST PDR_ON PDR_ON time MS19009V6 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. 2.2.
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Description STM32F405xx, STM32F407xx Two external ceramic capacitors should be connected on VCAP_1 & VCAP_2 pin. Refer to Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions. All packages have regulator ON feature. Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
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STM32F405xx, STM32F407xx Description The following conditions must be respected: Note: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.8 V (see Figure 10).
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Description STM32F405xx, STM32F407xx Figure 11. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization VDD PDR = 1.7 V or 1.8 V (2) VCAP_1/VCAP_2 V12 Min V12 time NRST PA0 asserted externally time ai18492d 1. This figure is valid both whatever the internal reset mode (onON or offOFF). 2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges. 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability Table 3.
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STM32F405xx, STM32F407xx Description has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison.
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Description STM32F405xx, STM32F407xx Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The standby mode is not supported when the embedded voltage regulator is bypassed and the V12 domain is controlled by an external power. 2.2.
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STM32F405xx, STM32F407xx Description Table 4.
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Description STM32F405xx, STM32F407xx General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F40x devices (see Table 4 for differences). • TIM2, TIM3, TIM4, TIM5 The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler.
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STM32F405xx, STM32F407xx Description SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 2.2.22 • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. Inter-integrated circuit interface (I²C) Up to three I²C bus interfaces can operate in multimaster and slave modes.
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Description STM32F405xx, STM32F407xx Table 5. USART feature comparison Max. baud rate Max. baud rate Smartcard in Mbit/s in Mbit/s (ISO 7816) (oversampling (oversampling by 16) by 8) USART name Standard features Modem (RTS/ CTS) USART1 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) USART2 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) USART3 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) UART4 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) UART5 X - X - X - 2.62 5.25 APB1 (max.
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STM32F405xx, STM32F407xx Description The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). 2.2.
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Description 2.2.29 STM32F405xx, STM32F407xx Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. 2.2.
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STM32F405xx, STM32F407xx 2.2.32 Description Digital camera interface (DCMI) The camera interface is not available in STM32F405xx devices. STM32F407xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features: 2.2.
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Description STM32F405xx, STM32F407xx connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.2.
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STM32F405xx, STM32F407xx Pinouts and pin description VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 12.
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Pinouts and pin description STM32F405xx, STM32F407xx 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 13.
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STM32F405xx, STM32F407xx Pinouts and pin description 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 14.
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Pinouts and pin description STM32F405xx, STM32F407xx 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 PI7 PI6 PI5 PI4 VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 VDD VSS PI3 PI2 Figure 15.
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STM32F405xx, STM32F407xx Pinouts and pin description Figure 16.
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Pinouts and pin description STM32F405xx, STM32F407xx Figure 17.
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STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
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Pinouts and pin description STM32F405xx, STM32F407xx Table 7.
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STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
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Pinouts and pin description STM32F405xx, STM32F407xx Table 7.
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STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
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Pinouts and pin description STM32F405xx, STM32F407xx Table 7.
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STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
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Pinouts and pin description STM32F405xx, STM32F407xx Table 7.
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STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
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Pinouts and pin description STM32F405xx, STM32F407xx Table 7.
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STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
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Pinouts and pin description STM32F405xx, STM32F407xx Table 7.
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STM32F405xx, STM32F407xx Pinouts and pin description Table 7.
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Pinouts and pin description STM32F405xx, STM32F407xx Table 8.
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STM32F405xx, STM32F407xx Pinouts and pin description Table 8.
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AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI PA0 TIM2_CH1_E TR TIM 5_CH1 TIM8_ETR USART2_CTS UART4_TX ETH_MII_CRS EVENTOUT PA1 TIM2_CH2 TIM5_CH2 USART2_RTS UART4_RX ETH_MII _RX_CLK ETH_RMII__REF _CLK EVENTOUT PA2 TIM2_CH3 TIM5_CH3 ETH_MDIO EVENTOUT ETH _MII_COL EVEN
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AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_ D1 ETH _MII_RXD2 EVENTOUT PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_ D2 ETH _MII_RXD3 EVENTOUT Port AF14 PB2 DocID022152 Rev 4 Port B EVENTOUT PB3 JTDO/ TRACES WO PB4 NJT
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AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port OTG_HS_ULPI_ STP PC0 PC1 Port C AF14 AF15 EVENTOUT ETH_MDC EVENTOUT OTG_HS_ULPI_ DIR ETH _MII_TXD2 EVENTOUT OTG_HS_ULPI_ NXT ETH _MII_TX_CLK EVENTOUT PC4 ETH_MII_RXD0 ETH_RMII_RXD0 EVENTOUT PC5 ETH _MII_RXD1 ETH _RMII_R
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AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port PD0 CAN1_RX PD1 PD2 CAN1_TX TIM3_ETR UART5_RX AF14 FSMC_D2 EVENTOUT FSMC_D3 SDIO_CMD AF15 EVENTOUT DCMI_D11 EVENTOUT PD3 USART2_CTS FSMC_CLK EVENTOUT PD4 USART2_RTS FSMC_NOE EVENTOUT PD5 USART2_TX FSMC_NWE EVENTOU
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AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI FSMC_NBL0 DCMI_D2 EVENTOUT FSMC_NBL1 DCMI_D3 EVENTOUT Port PE0 TIM4_ETR PE1 Port E AF14 AF15 PE2 TRACECL K PE3 TRACED0 FSMC_A19 PE4 TRACED1 FSMC_A20 DCMI_D4 EVENTOUT PE5 TRACED2 TIM9_CH1 FSMC_A21 DCMI_D6 EVENTOUT
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AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port AF14 AF15 PF0 I2C2_SDA FSMC_A0 EVENTOUT PF1 I2C2_SCL FSMC_A1 EVENTOUT PF2 I2C2_ SMBA FSMC_A2 EVENTOUT PF3 FSMC_A3 EVENTOUT PF4 FSMC_A4 EVENTOUT PF5 FSMC_A5 EVENTOUT PF6 TIM10_CH1 FSMC_NIORD EVENTOUT PF7 TIM11
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AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port PG0 Port G AF14 AF15 FSMC_A10 EVENTOUT PG1 FSMC_A11 EVENTOUT PG2 FSMC_A12 EVENTOUT PG3 FSMC_A13 EVENTOUT PG4 FSMC_A14 EVENTOUT PG5 FSMC_A15 EVENTOUT PG6 FSMC_INT2 EVENTOUT FSMC_INT3 EVENTOUT PG7 USART6_CK PG8
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AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port AF14 PH0 AF15 EVENTOUT PH1 EVENTOUT PH2 PH3 PH4 I2C2_SDA PH6 I2C2_SMB A PH7 I2C3_SCL EVENTOUT ETH _MII_COL EVENTOUT OTG_HS_ULPI_ NXT I2C2_SCL PH5 ETH _MII_CRS EVENTOUT EVENTOUT TIM12_CH1 ETH _MII_RXD2 STM32F405xx,
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AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port PI0 TIM5_CH4 PI1 PI2 Port I AF14 AF15 SPI2_NSS I2S2_WS DCMI_D13 EVENTOUT SPI2_SCK I2S2_CK DCMI_D8 EVENTOUT DCMI_D9 EVENTOUT DCMI_D10 EVENTOUT TIM8_CH4 SPI2_MISO PI3 TIM8_ETR SPI2_MOSI I2S2_SD I2S2ext_SD PI4 TIM8_B
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STM32F405xx, STM32F407xx 4 Memory mapping Memory mapping The memory map is shown in Figure 18. Figure 18.
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Memory mapping STM32F405xx, STM32F407xx Table 10.
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STM32F405xx, STM32F407xx Memory mapping Table 10.
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Memory mapping STM32F405xx, STM32F407xx Table 10.
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STM32F405xx, STM32F407xx Memory mapping Table 10.
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Electrical characteristics STM32F405xx, STM32F407xx 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32F405xx, STM32F407xx Power supply scheme Figure 21. Power supply scheme VBAT VBAT = 1.65 to 3.6V OUT GPIOs IN VCAP_1 VCAP_2 2 × 2.2 μF VDD VDD 1/2/...14/15 VSS 1/2/...14/15 15 × 100 nF + 1 × 4.7 μF Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) Power switch Level shifter 5.1.
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Electrical characteristics 5.1.7 STM32F405xx, STM32F407xx Current consumption measurement Figure 22. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device.
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STM32F405xx, STM32F407xx Electrical characteristics Table 12. Current characteristics Symbol Ratings Max.
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Electrical characteristics STM32F405xx, STM32F407xx Table 14. General operating conditions (continued) Symbol Parameter Min Typ Max Unit 1.08 1.14 1.20 V VOS bit in PWR_CR register= 1 Max frequency 168MHz 1.20 1.26 1.32 V Regulator OFF: 1.2 V external voltage must be supplied from external regulator on VCAP_1/VCAP_2 pins Max frequency 144MHz 1.10 1.14 1.20 V Max frequency 168MHz 1.20 1.26 1.30 V Input voltage on RST and FT pins(6) 2 V ≤ VDD ≤ 3.6 V –0.3 - 5.5 VDD ≤ 2 V –0.
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STM32F405xx, STM32F407xx Electrical characteristics Table 15. Limitations depending on the operating power supply range Operating power supply range ADC operation VDD =1.8 to 2.1 V(3) Conversion time up to 1.2 Msps VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps VDD = 2.4 to 2.7 V VDD = 2.7 to 3.6 V(5) Conversion time up to 2.4 Msps Conversion time up to 2.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 23. External capacitor CEXT C ESR R Leak MS19044V2 1. Legend: ESR is the equivalent series resistance. Table 16. VCAP_1/VCAP_2 operating conditions(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2 µF ESR ESR of external capacitor <2Ω 1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. 5.3.
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STM32F405xx, STM32F407xx Electrical characteristics Table 19. Embedded reset and power control block characteristics Symbol VPVD Parameter Conditions Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V PLS[2:0]=000 (falling edge) 1.98 2.04 2.08 V PLS[2:0]=001 (rising edge) 2.23 2.30 2.37 V PLS[2:0]=001 (falling edge) 2.13 2.19 2.25 V PLS[2:0]=010 (rising edge) 2.39 2.45 2.51 V PLS[2:0]=010 (falling edge) 2.29 2.35 2.39 V PLS[2:0]=011 (rising edge) 2.54 2.
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Electrical characteristics STM32F405xx, STM32F407xx Table 19. Embedded reset and power control block characteristics (continued) Symbol VBORhyst (1) Parameter Conditions Min Typ - 100 0.5 1.5 3.0 ms - 160 200 mA - - 5.4 µC BOR hysteresis TRSTTEMPO(1)(2) Reset temporization (1) InRush current on voltage regulator power-on (POR or wakeup from Standby) ERUSH(1) InRush energy on voltage regulator power-on (POR or wakeup from Standby) IRUSH VDD = 1.
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STM32F405xx, STM32F407xx Electrical characteristics Table 20.
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Electrical characteristics STM32F405xx, STM32F407xx Table 21.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF 50 45 40 IDD RUN(mA) 35 -45 °C 30 0 °C 25 25 °C 20 55 °C 85 °C 15 105 °C 10 5 0 0 20 40 60 80 100 120 140 160 180 CPU Frequency (MHz MS19974V1 Figure 25.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF 60 50 IDD RUN(mA) 40 -45°C 0°C 30 25°C 55°C 20 85°C 105°C 10 0 0 20 40 60 80 100 120 140 160 180 CPU Frequency (MHz MS19976V1 Figure 27.
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STM32F405xx, STM32F407xx Electrical characteristics Table 22.
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Electrical characteristics STM32F405xx, STM32F407xx Table 23. Typical and maximum current consumptions in Stop mode Typ Symbol Parameter Supply current in Stop mode with main regulator in Run mode IDD_STOP Supply current in Stop mode with main regulator in Low Power mode Conditions Max TA = 25 °C TA = 25 °C Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.45 1.5 11.00 20.
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STM32F405xx, STM32F407xx Electrical characteristics Table 25. Typical and maximum current consumptions in VBAT mode Max(1) Typ Symbol Parameter Backup IDD_VBA domain supply T current TA = 85 °C TA = 25 °C Conditions TA = 105 °C VBAT = 1.8 V VBAT= 2.4 V VBAT = 3.3 V VBAT = 3.6 V Backup SRAM ON, low-speed oscillator and RTC ON 1.29 1.42 1.68 6 11 Backup SRAM OFF, low-speed oscillator and RTC ON 0.62 0.73 0.96 3 5 Backup SRAM ON, RTC OFF 0.79 0.81 0.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 29. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) 6 5 IVBAT in (μA) 4 1.65V 1.8V 2V 3 2.4V 2.7V 3V 2 3.3V 3.6V 1 0 0 10 20 30 40 50 60 70 80 90 100 Temperature in (°C) MS19991V1 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic.
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STM32F405xx, STM32F407xx Electrical characteristics supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at
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Electrical characteristics STM32F405xx, STM32F407xx Table 26. Switching output I/O current consumption Symbol Parameter Conditions(1) I/O toggling frequency (fSW) Typ 2 MHz 0.02 8 MHz 0.14 25 MHz 0.51 50 MHz 0.86 60 MHz 1.30 2 MHz 0.10 8 MHz 0.38 25 MHz 1.18 50 MHz 2.47 60 MHz 2.86 2 MHz 0.17 8 MHz 0.66 25 MHz 1.70 50 MHz 2.65 60 MHz 3.48 2 MHz 0.23 8 MHz 0.95 25 MHz 3.20 50 MHz 4.69 60 MHz 8.06 2 MHz 0.30 8 MHz 1.22 25 MHz 3.90 50 MHz 8.
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STM32F405xx, STM32F407xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 27. The MCU is placed under the following conditions: • At startup, all I/O pins are configured as analog pins by firmware. • All peripherals are disabled unless otherwise mentioned • The code is running from Flash memory and the Flash memory access time is equal to 5 wait states at 168 MHz.
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Electrical characteristics STM32F405xx, STM32F407xx Table 27. Peripheral current consumption (continued) Peripheral(1) AHB3 APB1 168 MHz 144 MHz FSMC 2.18 1.67 TIM2 0.80 0.61 TIM3 0.58 0.44 TIM4 0.62 0.48 TIM5 0.79 0.61 TIM6 0.15 0.11 TIM7 0.16 0.12 TIM12 0.33 0.26 TIM13 0.27 0.21 TIM14 0.27 0.21 PWR 0.04 0.03 USART2 0.17 0.13 USART3 0.17 0.13 UART4 0.17 0.13 UART5 0.17 0.13 I2C1 0.17 0.13 I2C2 0.18 0.13 I2C3 0.18 0.13 (2) 0.17/0.16 0.13/0.
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STM32F405xx, STM32F407xx Electrical characteristics Table 27. Peripheral current consumption (continued) Peripheral(1) APB2 168 MHz 144 MHz SDIO 0.64 0.54 TIM1 1.47 1.14 TIM8 1.58 1.22 TIM9 0.68 0.54 TIM10 0.45 0.36 TIM11 0.47 0.38 (5) 2.20 2.10 ADC2(5) 2.04 1.93 (5) 2.10 2.00 SPI1 0.14 0.12 USART1 0.34 0.27 USART6 0.34 0.28 ADC1 ADC3 Unit mA 1. HSE oscillator with 4 MHz crystal and PLL are ON. 2.
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Electrical characteristics 5.3.8 STM32F405xx, STM32F407xx External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 29 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 29.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 30. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) t tW(HSE) THSE External clock source fHSE_ext OSC_IN IL STM32F ai17528 Figure 31.
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Electrical characteristics STM32F405xx, STM32F407xx Table 31. HSE 4-26 MHz oscillator characteristics(1) (2) Symbol fOSC_IN RF IDD gm tSU(HSE(3) Parameter Conditions Min Typ Max Unit Oscillator frequency 4 - 26 MHz Feedback resistor - 200 - kΩ VDD=3.3 V, ESR= 30 Ω, CL=5 pF@25 MHz - 449 - VDD=3.3 V, ESR= 30 Ω, CL=10 pF@25 MHz - 532 - Startup 5 - - mA/V VDD is stabilized - 2 - ms HSE current consumption Oscillator transconductance Startup time µA 1.
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STM32F405xx, STM32F407xx Electrical characteristics Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor - 18.4 - MΩ IDD LSE current consumption - - 1 µA gm Oscillator Transconductance 2.8 - - µA/V - 2 - s tSU(LSE)(2) startup time VDD is stabilized 1. Guaranteed by design, not tested in production. 2.
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Electrical characteristics STM32F405xx, STM32F407xx 1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Low-speed internal (LSI) RC oscillator Table 34. LSI oscillator characteristics (1) Symbol Parameter fLSI(2) tsu(LSI) Frequency Min Typ Max Unit 17 32 47 kHz (3) LSI oscillator startup time - 15 40 µs (3) LSI oscillator power consumption - 0.4 0.6 µA IDD(LSI) 1.
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STM32F405xx, STM32F407xx Electrical characteristics Table 35. Main PLL characteristics Symbol Parameter Min Typ Max Unit 0.95(2) 1 2.
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Electrical characteristics STM32F405xx, STM32F407xx Table 36. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max RMS - 90 - peak to peak - ±280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.
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STM32F405xx, STM32F407xx Electrical characteristics Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round [ ( ( 2 15 – 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ] fVCO_OUT must be expressed in MHz.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 36. PLL output clock waveforms in down spread mode Frequency (PLL_OUT) F0 2 x md tmode Time 2 x tmode ai17292 5.3.12 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 38. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode, VDD = 1.
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STM32F405xx, STM32F407xx Electrical characteristics Table 39. Flash memory programming (continued) Symbol tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Vprog Conditions Min(1) Typ Program/erase parallelism (PSIZE) = x 8 - 1200 2400 Program/erase parallelism (PSIZE) = x 16 - 700 1400 Program/erase parallelism (PSIZE) = x 32 - 550 1100 Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism (PSIZE) = x 16 - 1.3 2.
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Electrical characteristics STM32F405xx, STM32F407xx Table 40. Flash memory programming with VPP Symbol Parameter Conditions tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Min(1) Typ Max(1) Unit - 16 100(2) µs - 230 - - 490 - - 875 - - 6.9 - s 2.7 - 3.6 V TA = 0 to +40 °C VDD = 3.3 V VPP = 8.
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STM32F405xx, STM32F407xx Electrical characteristics A device reset allows normal operations to be resumed. The test results are given in Table 42. They are based on the EMS levels and classes defined in application note AN1709. Table 42. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.
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Electrical characteristics STM32F405xx, STM32F407xx Table 43. EMI characteristics Symbol Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 25/168 MHz VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from Flash with ART accelerator enabled SEMI 5.3.14 Peak level VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from Flash with ART accelerator and PLL spread spectrum enabled 0.
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STM32F405xx, STM32F407xx Electrical characteristics Table 45. Electrical sensitivities Symbol LU 5.3.15 Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation.
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Electrical characteristics STM32F405xx, STM32F407xx Table 47. I/O static characteristics Symbol VIL VIH (1) Parameter Conditions Min Typ Max TTL ports 2.7 V ≤ VDD ≤ 3.6 V - - 0.8 2.0 - - - - 0.
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STM32F405xx, STM32F407xx Electrical characteristics In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2. In particular: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 12).
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Electrical characteristics STM32F405xx, STM32F407xx Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 49.
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STM32F405xx, STM32F407xx Electrical characteristics Table 49. I/O AC characteristics(1)(2)(3) (continued) OSPEEDRy [1:0] bit value(1) Symbol Fmax(IO)ou t 11 tf(IO)out tr(IO)out - tEXTIpw Parameter Conditions Maximum frequency(4) Output high to low level fall time Output low to high level rise time Min Typ Max CL = 30 pF, VDD > 2.70 V - - 100(5) CL = 30 pF, VDD > 1.8 V - - 50(5) CL = 10 pF, VDD > 2.70 V - - 200(5) CL = 10 pF, VDD > 1.8 V - - TBD CL = 20 pF, 2.4 < VDD < 2.
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Electrical characteristics STM32F405xx, STM32F407xx Table 50. NRST pin characteristics Symbol VIL(NRST)(1) Parameter NRST Input low level voltage VIH(NRST)(1) NRST Input high level voltage VIL(NRST)(1) NRST Input low level voltage VIH(NRST)(1) NRST Input high level voltage Vhys(NRST) Min Typ Max TTL ports 2.7 V ≤ VDD ≤ 3.6 V - - 0.8 2 - - CMOS ports 1.8 V ≤ VDD ≤ 3.6 V NRST Schmitt trigger voltage hysteresis VF(NRST)(1) (1) TNRST_OUT Generated reset pulse duration 0.3VDD 0.
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STM32F405xx, STM32F407xx Electrical characteristics Table 51. Characteristics of TIMx connected to the APB1 domain(1) Symbol tres(TIM) Parameter Timer resolution time Conditions AHB/APB1 prescaler distinct from 1, fTIMxCLK = 84 MHz AHB/APB1 prescaler = 1, fTIMxCLK = 42 MHz fEXT ResTIM tCOUNTER Min Max Unit 1 - tTIMxCLK 11.9 - ns 1 - tTIMxCLK 23.
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Electrical characteristics STM32F405xx, STM32F407xx Table 52. Characteristics of TIMx connected to the APB2 domain(1) Symbol tres(TIM) Parameter Conditions Timer resolution time AHB/APB2 prescaler distinct from 1, fTIMxCLK = 168 MHz AHB/APB2 prescaler = 1, fTIMxCLK = 84 MHz fEXT ResTIM tCOUNTER Min Max Unit 1 - tTIMxCLK 5.95 - ns 1 - tTIMxCLK 11.
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STM32F405xx, STM32F407xx Electrical characteristics Table 53. I2C characteristics (continued) Standard mode I2C(1) Symbol Fast mode I2C(1)(2) Parameter Unit Min Max Min Max th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - μs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - μs Cb Capacitive load for each bus line - 400 - 400 pF µs 1.
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Electrical characteristics STM32F405xx, STM32F407xx Table 54. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 kΩ 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%.
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STM32F405xx, STM32F407xx Electrical characteristics Table 55. SPI dynamic characteristics(1) (continued) Symbol Parameter tw(SCKH) SCK high and low time tw(SCKL) Conditions Master mode, SPI presc = 2, 2.7V < VDD < 3.6V Master mode, SPI presc = 2, 1.7V < VDD < 3.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 40. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 41.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 42.
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Electrical characteristics STM32F405xx, STM32F407xx I2S interface characteristics Unless otherwise specified, the parameters given in Table 56 for the i2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 43. I2S slave timing diagram (Philips protocol) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 44.
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Electrical characteristics STM32F405xx, STM32F407xx Table 57. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 µs 1. Guaranteed by design, not tested in production. Table 58. USB OTG FS DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG FS operating voltage Min.(1) Typ. Max.(1) Unit 3.0(2) - 3.6 VDI(3) Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.
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STM32F405xx, STM32F407xx Electrical characteristics Table 59. USB OTG FS electrical characteristics(1) Driver characteristics Symbol Parameter Rise time(2) tr Fall time tf (2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Rise/ fall time matching trfm VCRS Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal.
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Electrical characteristics STM32F405xx, STM32F407xx 1. Guaranteed by design, not tested in production. Table 62. ULPI timing Value(1) Parameter Symbol Control in (ULPI_DIR) setup time tSC Control in (ULPI_NXT) setup time Unit Min. Max. - 2.0 - 1.5 Control in (ULPI_DIR, ULPI_NXT) hold time tHC 0 - Data in setup time tSD - 2.0 Data in hold time tHD 0 - Control out (ULPI_STP) setup time and hold time tDC - 9.2 Data out available from clock rising edge tDD - 10.7 ns 1.
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STM32F405xx, STM32F407xx Electrical characteristics Table 63. Ethernet DC electrical characteristics Symbol Input level Parameter VDD Min.(1) Max.(1) Unit 2.7 3.6 V Ethernet operating voltage 1. All the voltages are measured from the local ground potential. Table 64 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 47 shows the corresponding timing diagram. Figure 47.
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Electrical characteristics STM32F405xx, STM32F407xx Table 65. Dynamic characteristics: Ethernet MAC signals for RMII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 2 - - ns tih(RXD) Receive data hold time 1 - - ns tsu(CRS) Carrier sense set-up time 0.5 - - ns tih(CRS) Carrier sense hold time 2 - - ns td(TXEN) Transmit enable valid delay time 8 9.5 11 ns td(TXD) Transmit data valid delay time 8.5 10 11.
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STM32F405xx, STM32F407xx Electrical characteristics CAN (controller area network) interface Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 5.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 14. Table 67.
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Electrical characteristics STM32F405xx, STM32F407xx Table 67. ADC characteristics (continued) Symbol tCONV(4) Parameter Conditions Min Typ Max Unit fADC = 30 MHz 12-bit resolution 0.50 - 16.40 µs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 µs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 µs fADC = 30 MHz 6-bit resolution 0.30 - 16.
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STM32F405xx, STM32F407xx Electrical characteristics Table 68. ADC accuracy at fADC = 30 MHz(1) a Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 1.8(3) to 3.6 V Typ Max(2) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2.
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Electrical characteristics STM32F405xx, STM32F407xx EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 51. Typical connection diagram using the ADC STM32F VDD RAIN(1) Sample and hold ADC converter VT 0.6 V RADC(1) AINx VAIN Cparasitic VT 0.
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STM32F405xx, STM32F407xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 52 or Figure 53, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 52.
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Electrical characteristics 5.3.21 STM32F405xx, STM32F407xx Temperature sensor characteristics Table 69. Temperature sensor characteristics Symbol Parameter TL(1) Avg_Slope (1) V25(1) tSTART(2) TS_temp (3)(2) Min Typ Max Unit VSENSE linearity with temperature - ±1 ±2 °C Average slope - 2.5 mV/°C Voltage at 25 °C - 0.76 V Startup time - 6 10 µs 10 - - µs ADC sampling time when reading the temperature (1 °C accuracy) 1. Based on characterization, not tested in production.
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STM32F405xx, STM32F407xx 5.3.23 Electrical characteristics Embedded reference voltage The parameters given in Table 72 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 72. Embedded internal reference voltage Symbol VREFINT TS_vrefint(1) VRERINT_s(2) Parameter Internal reference voltage Conditions Min Typ –40 °C < TA < +105 °C 1.18 1.21 1.
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Electrical characteristics STM32F405xx, STM32F407xx Table 74. DAC characteristics (continued) Symbol Min Typ Max Unit DAC_OUT Lower DAC_OUT voltage min(2) with buffer OFF - 0.
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STM32F405xx, STM32F407xx Electrical characteristics Table 74. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s Wakeup time from off state tWAKEUP(4) (Setting the ENx bit in the DAC Control register) - 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones.
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Electrical characteristics STM32F405xx, STM32F407xx Asynchronous waveforms and timings Figure 55 through Figure 58 represent asynchronous waveforms and Table 75 through Table 78 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • AddressSetupTime = 1 • AddressHoldTime = 0x1 • DataSetupTime = 0x1 • BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. Figure 55.
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STM32F405xx, STM32F407xx Electrical characteristics Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.
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Electrical characteristics STM32F405xx, STM32F407xx Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid THCLK– 2 - ns - 1.
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STM32F405xx, STM32F407xx Electrical characteristics Table 77.
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Electrical characteristics STM32F405xx, STM32F407xx Table 78.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 59.
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Electrical characteristics STM32F405xx, STM32F407xx Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high FSMC_NWAIT valid after FSMC_CLK high th(CLKH-NWAIT) 0 - ns 4 - ns 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 60.
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STM32F405xx, STM32F407xx Electrical characteristics Table 80. Synchronous multiplexed PSRAM write timings(1)(2) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 0.
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Electrical characteristics STM32F405xx, STM32F407xx Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 0 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 2 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0.
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STM32F405xx, STM32F407xx Electrical characteristics Table 82. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol tw(CLK) d(CLKL-NExL) Parameter FSMC_CLK period Min Max Unit 2THCLK - ns t FSMC_CLK low to FSMC_NEx low (x=0..
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Electrical characteristics STM32F405xx, STM32F407xx Figure 63. PC Card/CompactFlash controller waveforms for common memory read access FSMC_NCE4_2(1) FSMC_NCE4_1 th(NCEx-AI) tv(NCEx-A) FSMC_A[10:0] th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) td(NREG-NCEx) td(NIORD-NCEx) FSMC_NREG FSMC_NIOWR FSMC_NIORD FSMC_NWE td(NCE4_1-NOE) FSMC_NOE tw(NOE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14895b 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Figure 64.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 th(NCE4_1-AI) High FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG FSMC_NWE td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0](1) ai14897b 1. Only data bits 0...7 are read (bits 8...15 are disregarded).
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Electrical characteristics STM32F405xx, STM32F407xx Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG td(NCE4_1-NWE) tw(NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 67.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NCE4_1 FSMC_NCE4_2 tv(NCEx-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD td(NCE4_1-NIOWR) tw(NIOWR) FSMC_NIOWR ATTxHIZ =1 th(NIOWR-D) tv(NIOWR-D) FSMC_D[15:0] ai14900c Table 83.
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Electrical characteristics STM32F405xx, STM32F407xx Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max Unit 8THCLK –1 - ns - 5THCLK– 1 ns 8THCLK– 2 - ns - 5THCLK+ 2.5 ns 5THCLK–1.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 69. NAND controller waveforms for read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE td(ALE-NOE) th(NOE-ALE) FSMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14901c Figure 70.
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Electrical characteristics STM32F405xx, STM32F407xx Figure 71. NAND controller waveforms for common memory read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) th(NOE-ALE) FSMC_NWE tw(NOE) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14912c Figure 72. NAND controller waveforms for common memory write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) tw(NWE) th(NOE-ALE) FSMC_NWE FSMC_NOE td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14913c Table 85.
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STM32F405xx, STM32F407xx Electrical characteristics Table 86.
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Electrical characteristics STM32F405xx, STM32F407xx Table 87. DCMI characteristics(1) (continued) Symbol Parameter Min Max 2.5 - tsu(DATA) Data input setup time th(DATA) Data hold time 1 - tsu(HSYNC), tsu(VSYNC) HSYNC/VSYNC input setup time 2 - th(HSYNC), th(VSYNC) HSYNC/VSYNC input hold time 0.5 - Unit ns 1. Data based on characterization results, not tested in production. 5.3.
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STM32F405xx, STM32F407xx Electrical characteristics Figure 75. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Table 88. Dynamic characteristics: SD / MMC characteristics(1) Symbol fPP Parameter Conditions Min Typ Max Unit 48 MHz - Clock frequency in data transfer mode 0 SDIO_CK/fPCLK2 frequency ratio - - 8/3 tW(CKL) Clock low time fpp = 48 MHz 8.5 9 - tW(CKH) Clock high time fpp = 48 MHz 8.
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Package characteristics STM32F405xx, STM32F407xx 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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STM32F405xx, STM32F407xx Package characteristics Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline e1 A1 ball location D e e Detail A E e2 G A2 F A Bump side Side view Wafer back side Detail A rotated by 90 °C A1 eee b Seating plane A0JW_ME Table 90. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.520 0.570 0.620 0.0205 0.0224 0.0244 A1 0.165 0.190 0.215 0.0065 0.
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Package characteristics STM32F405xx, STM32F407xx Figure 77. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline A A2 A1 E b E1 e D1 D c L1 L ai14398b 1. Drawing is not to scale. Table 91. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 Max 0.0630 0.150 0.0020 0.0059 1.400 1.450 0.0531 0.0551 0.0571 0.220 0.270 0.0067 0.0087 0.0106 0.
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STM32F405xx, STM32F407xx Package characteristics Figure 78. LQFP64 recommended footprint 48 33 0.3 49 12.7 32 0.5 10.3 10.3 64 17 1.2 1 16 7.8 12.7 ai14909 1. Drawing is not to scale. 2. Dimensions are in millimeters.
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Package characteristics STM32F405xx, STM32F407xx Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline c A1 A A2 SEATING PLANE C 0.25 mm GAUGE PLANE L D A1 K ccc C L1 D1 D3 51 75 50 100 E E3 E1 b 76 26 PIN 1 1 IDENTIFICATION 25 e 1L_ME_V4 1. Drawing is not to scale. Table 92. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data(1) millimeters inches Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.
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STM32F405xx, STM32F407xx Package characteristics Figure 80. LQFP100 recommended footprint 75 51 76 50 0.5 0.3 16.7 14.3 100 26 1.2 1 25 12.3 16.7 ai14906 1. Drawing is not to scale. 2. Dimensions are in millimeters.
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Package characteristics STM32F405xx, STM32F407xx Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline Seating plane C A A2 A1 c b 0.25 mm gage plane ccc C k D D1 A1 D3 L L1 108 73 72 109 E3 E1 144 E 37 Pin 1 identification 1 36 ME_1A e 1. Drawing is not to scale. Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 A1 0.050 A2 1.350 b 0.170 c 0.090 D 21.
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STM32F405xx, STM32F407xx Package characteristics Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol k Min Typ Max Min Typ Max 0° 3.5° 7° 0° 3.5° 7° ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 82. LQFP144 recommended footprint 108 109 73 1.35 72 0.35 0.5 17.85 19.9 144 22.6 37 1 36 19.9 22.6 ai14905c 1. Drawing is not to scale. 2.
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Package characteristics STM32F405xx, STM32F407xx Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline C Seating plane A2 ddd A1 C A A A1 ball A1 ball identifier index area e E F A F D e B R 15 BOTTOM VIEW 1 TOP VIEW Øb (176 + 25 balls) Ø eee M C A B Ø fff M C A0E7_ME_V4 1. Drawing is not to scale. Table 94. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.
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STM32F405xx, STM32F407xx Package characteristics Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline C Seating plane 0.25 mm gauge plane A A2 k c A1 ccc C A1 HD L D L1 ZD ZE 89 132 88 133 b E 176 Pin 1 identification HE 45 1 44 e 1T_ME 1. Drawing is not to scale. Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.600 Max 0.0630 A1 0.050 0.150 0.0020 A2 1.
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Package characteristics STM32F405xx, STM32F407xx Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max ccc Min Typ Max 0.080 k 0° 0.0031 7° 0° 7° 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 85. LQFP176 recommended footprint 1.2 1 176 133 132 0.5 21.8 26.7 0.3 44 45 89 88 1.2 21.8 26.7 1T_FP_V1 1. Dimensions are expressed in millimeters.
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STM32F405xx, STM32F407xx 6.2 Package characteristics Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
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Part numbering 7 STM32F405xx, STM32F407xx Part numbering Table 97.
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STM32F405xx, STM32F407xx Appendix A Application block diagrams USB OTG full speed (FS) interface solutions Figure 86. USB controller configured as peripheral-only and used in Full speed mode VDD 5V to VDD Volatge regulator (1) VBUS DM OSC_IN PA11//PB14 DP PA12/PB15 VSS OSC_OUT USB Std-B connector STM32F4xx MS19000V5 1. External voltage regulator only needed when building a VBUS powered device. 2.
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Application block diagrams STM32F405xx, STM32F407xx Figure 88. USB controller configured in dual mode and used in full speed mode VDD 5 V to VDD voltage regulator (1) VDD EN GPIO+IRQ Overcurrent Current limiter power switch(2) 5 V Pwr STM32F4xx VBUS PA9/PB13 DM PA11/PB14 OSC_IN OSC_OUT PA12/PB15 PA10/PB12 DP ID (3) VSS USBmicro-AB connector GPIO MS19002V3 1. External voltage regulator only needed when building a VBUS powered device. 2.
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STM32F405xx, STM32F407xx A.2 Application block diagrams USB OTG high speed (HS) interface solutions Figure 89. USB controller configured as peripheral, host, or dual-mode and used in high speed mode STM32F4xx FS PHY USB HS OTG Ctrl DP DM not connected DP ULPI_CLK DM ULPI_D[7:0] ULPI ID(2) ULPI_DIR VBUS ULPI_STP USB connector VSS ULPI_NXT High speed OTG PHY PLL XT1 24 or 26 MHz XT(1) MCO1 or MCO2 XI MS19005V2 1. It is possible to use MCO1 or MCO2 to save a crystal.
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Application block diagrams A.3 STM32F405xx, STM32F407xx Ethernet interface solutions Figure 90. MII mode using a 25 MHz crystal STM32 MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CRS MII_COL MCU Ethernet MAC 10/100 HCLK(1) Ethernet PHY 10/100 MII = 15 pins MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER IEEE1588 PTP Timer input trigger Timestamp TIM2 comparator MII + MDC = 17 pins MDIO MDC PPS_OUT(2) XTAL 25 MHz OSC HCLK PLL PHY_CLK 25 MHz MCO1/MCO2 XT1 MS19968V1 1. fHCLK must be greater than 25 MHz.
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STM32F405xx, STM32F407xx Application block diagrams Figure 92. RMII with a 25 MHz crystal and PHY with PLL STM32F Ethernet PHY 10/100 MCU RMII_TX_EN Ethernet MAC 10/100 RMII_TXD[1:0] RMII_RXD[1:0] HCLK(1) RMII_CRX_DV RMII_REF_CLK IEEE1588 PTP RMII = 7 pins REF_CLK MDIO Timer input trigger Timestamp TIM2 comparator RMII + MDC = 9 pins MDC /2 or /20 2.5 or 25 MHz synchronous 50 MHz XTAL 25 MHz OSC PLL HCLK PLL MCO1/MCO2 PHY_CLK 25 MHz XT1 MS19970V1 1. fHCLK must be greater than 25 MHz.
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Revision history 8 STM32F405xx, STM32F407xx Revision history Table 98. Document revision history Date Revision 15-Sep-2011 1 Initial release. 2 Added WLCSP90 package on cover page. Renamed USART4 and USART5 into UART4 and UART5, respectively. Updated number of USB OTG HS and FS in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts.
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STM32F405xx, STM32F407xx Revision history Table 98. Document revision history (continued) Date 24-Jan-2012 Revision Changes Added V12 in Table 19: Embedded reset and power control block characteristics. Updated Table 21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) and Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM.
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Revision history STM32F405xx, STM32F407xx Table 98. Document revision history (continued) Date 24-Jan-2012 178/185 Revision Changes Updated Table 61: USB HS clock timing parameters Updated Table 67: ADC characteristics. Updated Table 68: ADC accuracy at fADC = 30 MHz. Updated Note 1 in Table 74: DAC characteristics. Section 5.3.25: FSMC characteristics: updated Table 75 toTable 86, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms.
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STM32F405xx, STM32F407xx Revision history Table 98. Document revision history (continued) Date 31-May-2012 Revision Changes 3 Updated Figure 5: STM32F40x block diagram and Figure 7: Power supply supervisor interconnection with internal reset OFF Added SDIO, added notes related to FSMC and SPI/I2S in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Starting from Silicon revision Z, USB OTG full-speed interface is now available for all STM32F405xx devices.
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Revision history STM32F405xx, STM32F407xx Table 98. Document revision history (continued) Date 31-May-2012 180/185 Revision Changes Removed fHSE_ext typical value in Table 29: High-speed external user clock characteristics. Updated Table 31: HSE 4-26 MHz oscillator characteristics and Table 32: LSE oscillator characteristics (fLSE = 32.768 kHz). Added fPLL48_OUT maximum value in Table 35: Main PLL characteristics. Modified equation 1 and 2 in Section 5.3.
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STM32F405xx, STM32F407xx Revision history Table 98. Document revision history (continued) Date 04-Jun-2013 Revision Changes 4 Modified Note 1 below Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Figure 4 title. Updated Note 3 below Figure 21: Power supply scheme. Changed simplex mode into half-duplex mode in Section 2.2.25: Interintegrated sound (I2S). Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and DAC_OUT2, respectively.
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Revision history STM32F405xx, STM32F407xx Table 98. Document revision history (continued) Date 04-Jun-2013 Revision Changes Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline Updated Table 94: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.
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STM32F405xx, STM32F407xx Revision history Table 98. Document revision history (continued) Date 04-Jun-2013 Revision Changes Updated Figure 6: Multi-AHB matrix. Updated Figure 7: Power supply supervisor interconnection with internal reset OFF Changed 1.2 V to V12 in Section : Regulator OFF Updated LQFP176 pin 48. Updated Section 1: Introduction. Updated Section 2: Description. Updated operating voltage in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Note 1.
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Revision history STM32F405xx, STM32F407xx Table 98. Document revision history (continued) Date 04-Jun-2013 184/185 Revision Changes Updated Table 64: Dynamic characteristics: Ehternet MAC signals for SMI. Updated Table 66: Dynamic characteristics: Ethernet MAC signals for MII. Updated Table 79: Synchronous multiplexed NOR/PSRAM read timings. Updated Table 80: Synchronous multiplexed PSRAM write timings. Updated Table 81: Synchronous non-multiplexed NOR/PSRAM read 4 timings.
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STM32F405xx, STM32F407xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.