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STM32F20xxx Functional overview
177
The backup registers are 32-bit registers used to store 80 bytes of user application data
when V
DD
power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 3.18: Low-power
modes).
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the V
DD
supply when present or the V
BAT
pin.
3.18 Low-power modes
The STM32F20x family supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup.
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped when the device
enters the Stop or Standby mode.
3.19 V
BAT
operation
The V
BAT
pin allows to power the device V
BAT
domain from an external battery or an
external supercapacitor.
V
BAT
operation is activated when V
DD
is not present.
The V
BAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from V
BAT
, external interrupts and RTC alarm/events
do not exit it from V
BAT
operation.
When using WLCSP64+2 package, if IRROFF pin is connected to V
DD
, the V
BAT
functionality is no more available and V
BAT
pin should be connected to V
DD
.