Information

DocID15818 Rev 11 27/178
STM32F20xxx Functional overview
177
Figure 8. Startup in regulator OFF: slow V
DD
slope
- power-down reset risen after V
CAP_1
/V
CAP_2
stabilization
1. This figure is valid both whatever the internal reset mode (ON or OFF).
Figure 9. Startup in regulator OFF: fast V
DD
slope
- power-down reset risen before V
CAP_1
/V
CAP_2
stabilization
V
DD
time
1.08 V
PDR=1.8 V
V
CAP_1
/V
CAP_2
1.2 V
time
PA0 tied to NRST
NRST
V
DD
time
1.08 V
PDR=1.8 V
V
CAP_1
/V
CAP_2
1.2 V
time
PA0 asserted externally
NRST