Information

Revision history STM32F20xxx
174/178 DocID15818 Rev 11
29-Oct-2012 10
Changed minimum supply voltage from 1.65 to 1.8 V.
Updated number of AHB buses in Section 2: Description and
Section 3.12: Clocks and startup.
Removed Figure 4. Compatible board design between STM32F10xx
and STM32F2xx for LQFP176 package.
Updated Note 2 below Figure 4: STM32F20x block diagram.
Changed System memory to System memory + OTP in Figure 16:
Memory map.
Added Note 1 below Table 16: VCAP1/VCAP2 operating conditions.
Updated V
DDA
and V
REF+
decouping capacitor in Figure 19: Power
supply scheme and updated Note 3.
Changed simplex mode into half-duplex mode in Section 3.24: Inter-
integrated sound (I2S).
Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and
DAC_OUT2, respectively.Changed TIM2_CH1/TIM2_ETR into
TIM2_CH1_ETR for PA0 and PA5 in Table 10: Alternate function
mapping.
Updated note applying to I
DD
(external clock and all peripheral
disabled) in Table 21: Typical and maximum current consumption in
Run mode, code with data processing running from Flash memory
(ART accelerator disabled). Updated Note 3 below Table 22: Typical
and maximum current consumption in Sleep mode.
Removed f
HSE_ext
typical value in Table 28: High-speed external user
clock characteristics.
Updated master I2S clock jitter conditions and vlaues in Table 35:
PLLI2S (audio PLL) characteristics.
Updated equations in Section 6.3.11: PLL spread spectrum clock
generation (SSCG) characteristics.
Swapped TTL and CMOS port conditions for V
OL
and V
OH
in Tabl e 47:
Output voltage characteristics.
Updated V
IL(NRST)
and V
IH(NRST)
in Table 49: NRST pin
characteristics.
Updated Table 54: SPI characteristics and Table 55: I2S
characteristics. Removed note 1 related to measurement points below
Figure 42: SPI timing diagram - slave mode and CPHA = 1, Figure 43:
SPI timing diagram - master mode, and Figure 44: I2S slave timing
diagram (Philips protocol)(1).
Updated t
HC
in Table 61: ULPI timing.
Updated Figure 48: Ethernet SMI timing diagram, Table 63: Dynamics
characteristics: Ethernet MAC signals for SMI and Table 65: Dynamics
characteristics: Ethernet MAC signals for MII.
Update f
TRIG
in Table 66: ADC characteristics.
Updated I
DDA
description in Table 68: DAC characteristics.
Updated note below Figure 53: Power supply and reference
decoupling (VREF+ not connected to VDDA) and Figure 54: Power
supply and reference decoupling (VREF+ connected to VDDA).
Table 95. Document revision history (continued)
Date Revision Changes