Information

DocID15818 Rev 11 17/178
STM32F20xxx Description
177
Figure 4. STM32F20x block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 120 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 60 MHz.
2. The camera interface and Ethernet are available only in STM32F207xx devices.
GPIO PORT A
AHB/APB2
EXT IT. WKUP
140 AF
PA[15:0]
GPIO PORT B
PB[15:0]
TIM1 / PWM
4 compl. channels (TIM1_CH[1:4]N)
4 channels (TIM1_CH[1:4]), ETR,
BKIN as AF
TIM8 / PWM
GPIO PORT C
PC[15:0]
USART 1
RX, TX, CK,
CTS, RTS as AF
GPIO PORT D
PD[15:0]
GPIO PORT E
PE[15:0]
GPIO PORT F
PF[15:0]
GPIO PORT G
PG[15:0]
SPI1
MOSI, MISO
SCK, NSS as AF
APB2 60MHz
APB1 30MHz
8 analog inputs common
to the 3 ADCs
8 analog inputs common
to the ADC1 & 2
V
DDREF_ADC
8 analog inputs to ADC3
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
4 channels
RX, TX, CK,
USART2
RX, TX, CK
USART3
RX, TX as AF
UART4
RX, TX as AF
UART5
MOSI/DOUT, MISO/DIN, SCK/CK
SPI2/I2S2
NSS/WS, MCK as AF
MOSI/DOUT, MISO/DIN, SCK/CK
SPI3/I2S3
NSS/WS, MCK as AF
SCL, SDA, SMBA as AF
I2C1/SMBUS
SCL, SDA, SMBA as AF
I2C2/SMBUS
TX, RX
bxCAN1
TX, RX
bxCAN2
DAC1_OUT
as AF
DAC2_OUT
as AF
ITF
WWDG
4 KB BKSPRAM
RTC_AF1
OSC32_IN
OSC_IN
OSC_OUT
OSC32_OUT
NRST
V
DDA
, V
SSA
V
CAP1,
V
CAP2
USART 6
RX, TX, CK,
CTS, RTS as AF
smcard
irDA
smcard
irDA
smcard
irDA
smcard
irDA
16b
16b
32b
16b
16b
32b
16b
16b
CTS, RTS as AF
CTS, RTS as AF
SDIO / MMC
D[7:0]
CMD, CK as AF
V
BAT
= 1.65 to 3.6 V
DMA1
AHB/APB1
DMA2
SCL, SDA, SMBA as AF
I2C3/SMBUS
GPIO PORT H
PH[15:0]
GPIO PORT I
PI[11:0]
JTAG & SW
D-BUS
S-BUS
I-BUS
NVIC
ETM
MPU
NJTRST, JTDI,
JTDO/SWD
JTDO/TRACESWO
TRACECLK
TRACED[3:0]
JTCK/SWCLK
Ethernet MAC
DMA/
MII or RMII as AF
MDIO as AF
FIFO
10/100
USB
DMA/
FIFO
OTG HS
DP, DM
ULPI: CK, D(7:0), DIR, STP, NXT
DMA2
8 Streams
FIFO
DMA1
8 Streams
FIFO
ACCEL/
CACHE
SRAM 112 KB
SRAM 16 KB
CLK, NE [3:0], A[23:0]
D[31:0], OEN, WEN,
NBL[3:0], NL, NREG
NWAIT/IORDY, CD
NIORD, IOWR, INT[2:3]
INTN, NIIS16 as AF
SCL, SDA, INTN, ID, VBUS, SOF
Camera
interface
HSYNC, VSYNC
PIXCLK, D[13:0]
USB
PHY
OTG FS
DP
DM
FIFO
FIFO
AHB1 120 MHz
PHY
FIFO
USART 2MBps
Temperature sensor
ADC1
ADC2
ADC 3
IF
IF
@VDDA
@VDDA
POR/PDR/
Supply
@VDDA
supervision
PVD
Reset
Int
POR
XTAL OSC
4- 26 MHz
XTAL 32 kHz
HCLKx
MANAGT
RTC
RC HS
FCLK
RC LS
PWR
IWDG
@V
BAT
@VDDA
@VDD
AWU
Reset &
clock
control
PLL1&2
PCLKx
interface
V
DD
= 1.8 to 3.6 V
V
SS
Voltage
regulator
3.3 V to 1.2 V
V
DD12
Power managmt
@VDD
RTC_AF1
Backup register
SCL/SDA, INTN, ID, VBUS, SOF
AHB bus-matrix 8S7M
APB2 60MHz
AHB2 120 MHz
LSLS
2 channels as AF
1 channel as AF
1 channel as AF
TIM14
16b
16b
16b
TIM9
2 channels as AF
TIM10
1 channel as AF
16b
16b
TIM11
1 channel as AF
16b
BOR
DAC1
DAC2
Flash
1 Mbyte
SRAM, PSRAM, NOR Flash,
PC Card (ATA), NAND Flash
External memory
controller (FSMC)
TIM6
TIM7
TIM2
TIM3
TIM4
TIM5
TIM12
TIM13
ai17614c
4 compl. channels (TIM1_CH[1:4]N)
4 channels (TIM1_CH[1:4]), ETR,
BKIN as AF
FIFO
RNG
ARM Cortex-M3
120 MHz
ART accelerator
APB1 30MHz
AHB3