Information

DocID15818 Rev 11 167/178
STM32F20xxx Revision history
177
25-Nov-2010 5
Update I/Os in Section : Features.
Added WLCSP64+2 package. Added note 1 related to LQFP176 on
cover page.
Added trademark for
ART accelerator. Updated Section 3.2:
Adaptive real-time memory accelerator (ART Accelerator™).
Updated Figure 5: Multi-AHB matrix.
Added case of BOR inactivation using IRROFF on WLCSP devices in
Section 3.15: Power supply supervisor.
Reworked Section 3.16: Voltage regulator to clarify regulator off
modes. Renamed PDROFF, IRROFF in the whole document.
Added Section 3.19: VBAT operation.
Updated LIN and IrDA features for UART4/5 in Table 6: U SART
feature comparison.
Table 8: STM32F20x pin and ball definitions: Modified V
DD_3
pin, and
added note related to the FSMC_NL pin; renamed BYPASS-REG
REGOFF, and add IRROFF pin; renamed USART4/5 UART4/5.
USART4 pins renamed UART4.
Changed V
SS_SA
to V
SS
, and V
DD_SA
pin reserved for future use.
Updated maximum HSE crystal frequency to 26 MHz.
Section 6.2: Absolute maximum ratings: Updated V
IN
minimum and
maximum values and note related to five-volt tolerant inputs in
Table 11: Voltage characteristics. Updated I
INJ(PIN)
maximum values
and related notes in Table 12: Current characteristics.
Updated V
DDA
minimum value in Table 14: General operating
conditions.
Added Note 2 and updated Maximum CPU frequency in Table 15:
Limitations depending on the operating power supply range, and
added Figure 21: Number of wait states versus fCPU and VDD range.
Added brownout level 1, 2, and 3 thresholds in Table 19: Embedded
reset and power control block characteristics.
Changed f
OSC_IN
maximum value in Table 30: HSE 4-26 MHz
oscillator characteristics.
Changed f
PLL_IN
maximum value in Table 34: Main PLL
characteristics, and updated jitter parameters in Table 35: PLLI2S
(audio PLL) characteristics.
Section 6.3.16: I/O port characteristics: updated V
IH
and V
IL
in
Table 48: I/O AC characteristics.
Added Note 1 below Table 47: Output voltage characteristics.
Updated R
PD
and R
PU
parameter description in Table 57: USB OTG
FS DC electrical characteristics.
Updated V
REF+
minimum value in Table 66: ADC characteristics.
Updated Table 71: Embedded internal reference voltage.
Removed Ethernet and USB2 for 64-pin devices in Table 10 1: Mai n
applications versus package for STM32F2xxx microcontrollers.
Added A.2: USB OTG full speed (FS) interface solutions, removed
“OTG FS connection with external PHY” figure, updated Figure 87,
Figure 88, and Figure 90 to add STULPI01B.
Table 95. Document revision history (continued)
Date Revision Changes