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DocID15818 Rev 11 137/178
STM32F20xxx Electrical characteristics
177
Figure 61. Synchronous multiplexed PSRAM write timings
Table 77. Synchronous multiplexed PSRAM write timings
(1)(2)
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 2T
HCLK
- 1 - ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns
t
d(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x= 0…2) 2 - ns
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low - 2 ns
t
d(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high 3 - ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns
t
d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x=16…25) 7 - ns
t
d(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low - 1 ns
t
d(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high 0 - ns
t
d(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns
t
d(CLKL-DATA
) FSMC_A/D[15:0] valid data after FSMC_CLK low - 2 ns
t
d(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high 0.5 - ns
FSMC_CLK
FSMC_NEx
FSMC_NADV
FSMC_A[25:16]
FSMC_NWE
FSMC_AD[15:0] AD[15:0] D1 D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 0
BUSTURN = 0
t
d(CLKL-NExL)
t
d(CLKL-NExH)
t
d(CLKL-NADVL)
t
d(CLKL-AV)
t
d(CLKL-NADVH)
t
d(CLKL-AIV)
t
d(CLKL-NWEH)
t
d(CLKL-NWEL)
t
d(CLKL-NBLH)
t
d(CLKL-ADV)
t
d(CLKL-ADIV)
t
d(CLKL-Data)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
ai14992g
t
d(CLKL-Data)
FSMC_NBL