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DocID15818 Rev 11 115/178
STM32F20xxx Electrical characteristics
177
Figure 44. I
2
S slave timing diagram (Philips protocol)
(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 45. I
2
S master timing diagram (Philips protocol)
(1)
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
CK Input
CPOL = 0
CPOL = 1
t
c(CK)
WS input
SD
transmit
SD
receive
t
w(CKH)
t
w(CKL)
t
su(WS)
t
v(SD_ST)
t
h(SD_ST)
t
h(WS)
t
su(SD_SR)
t
h(SD_SR)
MSB receive Bitn receive LSB receive
MSB transmit Bitn transmit LSB transmit
ai14881b
LSB receive
(2)
LSB transmit
(2)
CK output
CPOL = 0
CPOL = 1
t
c(CK)
WS output
SD
receive
SD
transmit
t
w(CKH)
t
w(CKL)
t
su(SD_MR)
t
v(SD_MT)
t
h(SD_MT)
t
h(WS)
t
h(SD_MR)
MSB receive Bitn receive LSB receive
MSB transmit Bitn transmit LSB transmit
ai14884b
t
f(CK)
t
r(CK)
t
v(WS)
LSB receive
(2)
LSB transmit
(2)