Information

Electrical characteristics STM32F20xxx
114/178 DocID15818 Rev 11
Table 55. I
2
S characteristics
Symbol Parameter Conditions Min Max Unit
f
CK
1/t
c(CK)
I
2
S clock frequency
Master, 16-bit data,
audio frequency = 48 kHz, main
clock disabled
1.23 1.24
MHz
Slave 0 64F
S
(1)
t
r(CK)
t
f(CK)
I
2
S clock rise and fall time capacitive load C
L
= 50 pF -
(2)
ns
t
v(WS)
(3)
WS valid time Master 0.3 -
t
h(WS)
(3)
WS hold time Master 0 -
t
su(WS)
(3)
WS setup time Slave 3 -
t
h(WS)
(3)
WS hold time Slave 0 -
t
w(CKH)
(3)
t
w(CKL)
(3)
CK high and low time Master f
PCLK
= 30 MHz 396 -
t
su(SD_MR)
(3)
t
su(SD_SR)
(3)
Data input setup time
Master receiver
Slave receiver
45
0
-
t
h(SD_MR)
(3)(4)
t
h(SD_SR)
(3)(4)
Data input hold time
Master receiver: f
PCLK
= 30 MHz,
Slave receiver: f
PCLK
= 30 MHz
13
0
-
t
v(SD_ST)
(3)(4)
Data output valid time
Slave transmitter (after enable
edge)
- 30
t
h(SD_ST)
(3)
Data output hold time
Slave transmitter (after enable
edge)
10 -
t
v(SD_MT)
(3)(4)
Data output valid time
Master transmitter (after enable
edge)
- 6
t
h(SD_MT)
(3)
Data output hold time
Master transmitter (after enable
edge)
0-
1. F
S
is the sampling frequency. Refer to the I2S section of the STM32F20xxx/21xxx reference manual for more details. f
CK
values reflect only the digital peripheral behavior which leads to a minimum of (I2SDIV/(2*I2SDIV+ODD), a maximum of
(I2SDIV+ODD)/(2*I2SDIV+ODD) and F
S
maximum values for each mode/condition.
2. Refer to Table 48: I/O AC characteristics.
3. Based on design simulation and/or characterization results, not tested in production.
4. Depends on f
PCLK
. For example, if f
PCLK
=8 MHz, then T
PCLK
= 1/f
PLCLK
=125 ns.