Information

DocID15818 Rev 11 113/178
STM32F20xxx Electrical characteristics
177
Figure 43. SPI timing diagram - master mode
ai14136V2
SCK Output
CPHA= 0
MOSI
OUTPUT
MISO
INP UT
CPHA= 0
MSBIN
M SB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
B I T1 OUT
NSS input
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(MI)
High
SCK Output
CPHA=1
CPHA=1
CPOL=0
CPOL=1
t
su(MI)
t
v(MO)
t
h(MO)