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DocID15274 Rev 7 95/104
STM32F105xx, STM32F107xx Application block diagrams
103
Figure 52. RMII with a 25 MHz crystal
1. The NS DP83848 is recommended as the input jitter requirement of this PHY. It is compliant with the output
jitter specification of the MCU.
MCU
Ethernet
MAC 10/100
Ethernet
PHY 10/100
PLLS
XT1/XT2
RMII_RXD[1:0]
RMII_CRX_DV
RMII_REF_CLK
RMII_TX_EN
RMII_TXD[1:0]
MDIO
MDC
HCLK
STM32F107xx
TIM2
Time stamp
comparator
Timer
input
trigger
IEEE1588 PTP
RMII
= 7 pins
RMII + MDC
= 9 pins
ai15659b
50 MHz
XTAL
25 MHz
OSC
NS DP83848
(1)
50 MHz
50 MHz