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DocID15274 Rev 7 7/104
STM32F105xx, STM32F107xx List of figures
8
List of figures
Figure 1. STM32F105xx and STM32F107xx connectivity line block diagram . . . . . . . . . . . . . . . . . 12
Figure 2. STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view. . . . . . . . 23
Figure 3. STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout . . . . . . . . . . . . . . 24
Figure 4. STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout . . . . . . . . . . . . . . . 25
Figure 5. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 6. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 7. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 8. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 10. Typical current consumption on V
BAT
with RTC on vs. temperature at
different V
BAT
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. Typical current consumption in Stop mode with regulator in Run mode
versus temperature at different V
DD
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. Typical current consumption in Stop mode with regulator in Low-power
mode versus temperature at different V
DD
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 13. Typical current consumption in Standby mode versus temperature at
different V
DD
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 15. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 16. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 18. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 19. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 20. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 21. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 22. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 24. I
2
C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 25. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 26. SPI timing diagram - slave mode and CPHA = 1
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 27. SPI timing diagram - master mode
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 28. I
2
S slave timing diagram (Philips protocol)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 29. I
2
S master timing diagram (Philips protocol)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 30. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . 71
Figure 31. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 32. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 33. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 34. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 35. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 36. Power supply and reference decoupling (V
REF+
not connected to V
DDA
). . . . . . . . . . . . . . 78
Figure 37. Power supply and reference decoupling (V
REF+
connected to V
DDA
). . . . . . . . . . . . . . . . . 78
Figure 38. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 39. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 40. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 84
Figure 41. LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 42. Recommended footprint
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 43. LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 86