Information

Electrical characteristics STM32F105xx, STM32F107xx
66/104 DocID15274 Rev 7
I
2
S - SPI interface characteristics
Unless otherwise specified, the parameters given in Table 43 for SPI or in Table 44 for I
2
S
are derived from tests performed under the ambient temperature, f
PCLKx
frequency and V
DD
supply voltage conditions summarized in Table 9.
Refer to Section 5.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK,
SD for I
2
S).
Table 43. SPI characteristics
Symbol Parameter Conditions Min Max Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master mode - 18
MHz
Slave mode - 18
t
r(SCK)
t
f(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF - 8 ns
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode 30 70 %
t
su(NSS)
NSS setup time Slave mode 4 t
PCLK
-
ns
t
h(NSS)
NSS hold time Slave mode 2 t
PCLK
-
t
w(SCKH)
t
w(SCKL)
SCK high and low time
Master mode, f
PCLK
= 36 MHz,
presc = 4
50 60
t
su(MI)
Data input setup time
Master mode 4 -
t
su(SI)
Slave mode 5 -
t
h(MI)
Data input hold time
Master mode 5 -
t
h(SI)
Slave mode 5 -
t
a(SO)
Data output access
time
Slave mode, f
PCLK
= 20 MHz - 3*t
PCLK
t
v(SO)
Data output valid time Slave mode (after enable edge) - 34
t
v(MO)
Data output valid time Master mode (after enable edge) - 8
t
h(SO)
Data output hold time
Slave mode (after enable edge) 32 -
t
h(MO)
Master mode (after enable edge) 10 -