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DocID15274 Rev 7 57/104
STM32F105xx, STM32F107xx Electrical characteristics
103
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 18 and Figure 19 for standard I/Os, and
in Figure 20 and Figure 21 for 5 V tolerant I/Os.
V
IH
Standard IO input high
level voltage
- 0.41*(V
DD
-2 V)+1.3 V - V
DD
+0.3 V
IO FT
(1)
input high level
voltage
V
DD
> 2 V
0.42*(V
DD
-2 V)+1 V -
5.5
V
V
DD
≤ 2 V 5.2
V
hys
Standard IO Schmitt
trigger voltage
hysteresis
(2)
- 200 - - mV
IO FT Schmitt trigger
voltage hysteresis
(2)
- 5% V
DD
(3)
- - mV
I
lkg
Input leakage current
(4)
V
SS
≤V
IN
≤V
DD
Standard I/Os
- - ±1
µA
V
IN
= 5 V, I/O FT - - 3
R
PU
Weak pull-
up
equivalent
resistor
(5)
All pins
except for
PA10
V
IN
= V
SS
30 40 50
kΩ
PA10 8 11 15
R
PD
Weak pull-
down
equivalent
resistor
(5)
All pins
except for
PA10
V
IN
= V
DD
30 40 50
kΩ
PA10 8 11 15
C
IO
I/O pin capacitance - - 5 - pF
1. FT = Five-volt tolerant. In order to sustain a voltage higher than V
DD
+0.3 the internal pull-up/pull-down resistors must be
disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution
to the series resistance is minimum (~10% order).
Table 36. I/O static characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit