Information

Electrical characteristics STM32F105xx, STM32F107xx
52/104 DocID15274 Rev 7
All timings are derived from tests performed under ambient temperature and V
DD
supply
voltage conditions summarized in Table 9.
5.3.8 PLL, PLL2 and PLL3 characteristics
The parameters given in Table 27 and Table 28 are derived from tests performed under
temperature and V
DD
supply voltage conditions summarized in Table 9.
Table 26. Low-power mode wakeup timings
Symbol Parameter Typ Unit
t
WUSLEEP
(1)
1. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
Wakeup from Sleep mode 1.8 µs
t
WUSTOP
(1)
Wakeup from Stop mode (regulator in run mode) 3.6
µs
Wakeup from Stop mode (regulator in low power mode) 5.4
t
WUSTDBY
(1)
Wakeup from Standby mode 50 µs
Table 27. PLL characteristics
Symbol Parameter Min
(1)
1. Based on characterization, not tested in production.
Max
(1)
Unit
f
PLL_IN
PLL input clock
(2)
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by f
PLL_OUT
.
312MHz
Pulse width at high level 30 - ns
f
PLL_OUT
PLL multiplier output clock 18 72 MHz
f
VCO_OUT
PLL VCO output 36 144 MHz
t
LOCK
PLL lock time - 350 µs
Jitter Cycle-to-cycle jitter - 300 ps
Table 28. PLL2 and PLL3 characteristics
Symbol Parameter Min
(1)
1. Based on characterization, not tested in production.
Max
(1)
Unit
f
PLL_IN
PLL input clock
(2)
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by f
PLL_OUT
.
35MHz
Pulse width at high level 30 - ns
f
PLL_OUT
PLL multiplier output clock 40 74 MHz
f
VCO_OUT
PLL VCO output 80 148 MHz
t
LOCK
PLL lock time - 350 µs
Jitter Cycle-to-cycle jitter - 400 ps