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This is information on a product in full production.

March 2014 DocID15274 Rev 7 1/104

STM32F105xx

STM32F107xx

Connectivity line, ARM

-based 32-bit MCU with 64/256 KB Flash, USB

OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces

Datasheet - production data

Features

• Core: ARM

32-bit Cortex

-M3 CPU

– 72 MHz maximum frequency, 1.25

DMIPS/MHz (Dhrystone 2.1) performance

at 0 wait state memory access

– Single-cycle multiplication and hardware division

• Memories

– 64 to 256 Kbytes of Flash memory

– 64 Kbytes of general-purpose SRAM

• Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage

detector (PVD)

– 3-to-25 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC with calibration

– 32 kHz oscillator for RTC with calibration

• Low power

– Sleep, Stop and Standby modes

– VBAT supply for RTC and backup registers

• 2 × 12-bit, 1 µs A/D converters (16 channels)

– Conversion range: 0 to 3.6 V

– Sample and hold capability

– Temperature sensor

– up to 2 MSPS in interleaved mode

• 2 × 12-bit D/A converters

• DMA: 12-channel DMA controller

– Supported peripherals: timers, ADCs, DAC,

I2Ss, SPIs, I2Cs and USARTs

• Debug mode

– Serial wire debug (SWD) & JTAG interfaces

–Cortex

-M3 Embedded Trace Macrocell™

• Up to 80 fast I/O ports

– 51/80 I/Os, all mappable on 16 external

interrupt vectors and almost all 5 V-tolerant

• CRC calculation unit, 96-bit unique ID

• Up to 10 timers with pinout remap capability

– Up to four 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

– 1 × 16-bit motor control PWM timer with

dead-time generation and emergency stop

– 2 × watchdog timers (Independent and

Window)

– SysTick timer: a 24-bit downcounter

– 2 × 16-bit basic timers to drive the DAC

• Up to 14 communication interfaces with pinout

remap capability

– Up to 2 × I2C interfaces (SMBus/PMBus)

– Up to 5 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Up to 3 SPIs (18 Mbit/s), 2 with a

multiplexed I2S interface that offers audio

class accuracy via advanced PLL schemes

– 2 × CAN interfaces (2.0B Active) with 512

bytes of dedicated SRAM

– USB 2.0 full-speed device/host/OTG controller

with on-chip PHY that supports HNP/SRP/ID

with 1.25 Kbytes of dedicated SRAM

– 10/100 Ethernet MAC with dedicated DMA

and SRAM (4 Kbytes): IEEE1588 hardware

support, MII/RMII available on all packages

Table 1. Device summary

Reference Part number

STM32F105xx

STM32F105R8, STM32F105V8

STM32F105RB, STM32F105VB

STM32F105RC, STM32F105VC

STM32F107xx

STM32F107RB, STM32F107VB

STM32F107RC, STM32F107VC

LQFP100 14 × 14 mm

LQFP64 10 × 10 mm

FBGA

LFBGA100 10 × 10 mm

www.st.com

Summary of content (104 pages)

PAGE 1
STM32F105xx STM32F107xx Connectivity line, ARM®-based 32-bit MCU with 64/256 KB Flash, USB OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces Datasheet - production data Features FBGA ® ® • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.
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Contents STM32F105xx, STM32F107xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2/104 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.
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STM32F105xx, STM32F107xx 2.3.29 Contents Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 Parameter conditions . . . . . . . . . . . . . . . . .
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Contents 6 7 STM32F105xx, STM32F107xx Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.2.2 Selecting the product temperature range .
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STM32F105xx, STM32F107xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . .
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List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. 6/104 STM32F105xx, STM32F107xx USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F105xx, STM32F107xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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List of figures Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. 8/104 STM32F105xx, STM32F107xx Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 USB OTG FS device mode. . . . . . . . . . . . . . . . . . . . . . .
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STM32F105xx, STM32F107xx 1 Introduction Introduction This datasheet provides the description of the STM32F105xx and STM32F107xx connectivity line microcontrollers. For more details on the whole STMicroelectronics STM32F10xxx family, please refer to Section 2.2: Full compatibility throughout the family. The STM32F105xx and STM32F107xx datasheet should be read in conjunction with the STM32F10xxx reference manual.
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Description 2.1 STM32F105xx, STM32F107xx Device overview Figure 1 shows the general block diagram of the device family. Table 2.
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STM32F105xx, STM32F107xx 2.2 Description Full compatibility throughout the family The STM32F105xx and STM32F107xx constitute the connectivity line family whose members are fully pin-to-pin, software and feature compatible.
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Description 2.3 STM32F105xx, STM32F107xx Overview Figure 1. STM32F105xx and STM32F107xx connectivity line block diagram TPIU SW/JTAG ETM Trace/Trig Ibus Cortex-M3 CPU GP DMA1 Ethernet MAC 10/100 DMA Ethernet NRST VDDA VSSA @VDD XTAL osc 3-25 MHz OSC_IN OSC_OUT C_O IWDG PCLK1 PCLK2 HCLK FCLK PLL3 Standby interface @V VBAT =1.8 V to 3.
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STM32F105xx, STM32F107xx 2.3.1 Description ARM Cortex-M3 core with embedded Flash and SRAM The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
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Description 2.3.6 STM32F105xx, STM32F107xx External interrupt/event controller (EXTI) The external interrupt/event controller consists of 20 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period.
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STM32F105xx, STM32F107xx 2.3.9 2.3.10 Description Power supply schemes • VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. • VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.8 to 3.
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Description STM32F105xx, STM32F107xx • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.
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STM32F105xx, STM32F107xx 2.3.15 Description Timers and watchdogs The STM32F105xx and STM32F107xx devices include an advanced-control timer, four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the general-purpose and basic timers. Table 4.
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Description STM32F105xx, STM32F107xx Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler.
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STM32F105xx, STM32F107xx Description USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5. 2.3.18 Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes.
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Description 2.3.21 STM32F105xx, STM32F107xx • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal FIFOs to buffer transmit and receive frames.
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STM32F105xx, STM32F107xx 2.3.24 Description Remap capability This feature allows the use of a maximum number of peripherals in a given application. Indeed, alternate functions are available not only on the default pins but also on other specific pins onto which they are remappable. This has the advantage of making board design and port usage much more flexible. For details refer to Table 5: Pin definitions; it shows the list of remappable alternate functions and the pins onto which they can be remapped.
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Description STM32F105xx, STM32F107xx Eight DAC trigger inputs are used in the STM32F105xx and STM32F107xx connectivity line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 2.3.27 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V.
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STM32F105xx, STM32F107xx 3 Pinouts and pin description Pinouts and pin description Figure 2.
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Pinouts and pin description STM32F105xx, STM32F107xx 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 3.
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STM32F105xx, STM32F107xx Pinouts and pin description VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 4.
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Pinouts and pin description STM32F105xx, STM32F107xx Table 5.
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STM32F105xx, STM32F107xx Pinouts and pin description Table 5.
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Pinouts and pin description STM32F105xx, STM32F107xx Table 5.
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STM32F105xx, STM32F107xx Pinouts and pin description Table 5.
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Pinouts and pin description STM32F105xx, STM32F107xx Table 5.
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STM32F105xx, STM32F107xx Pinouts and pin description 1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT = 5 V tolerant. All I/Os are VDD capable. 3. Function availability depends on the chosen device. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5.
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Memory mapping 4 STM32F105xx, STM32F107xx Memory mapping The memory map is shown in Figure 5. Figure 5.
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STM32F105xx, STM32F107xx Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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Electrical characteristics 5.1.6 STM32F105xx, STM32F107xx Power supply scheme Figure 8. Power supply scheme VBAT Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) OUT GP I/Os IN Level shifter Po wer swi tch 1.8-3.6V IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4/5 5 × 100 nF + 1 × 4.7 µF VDD 1/2/3/4/5 VDDA VREF 10 nF + 1 µF Regulator VSS 10 nF + 1 µF VREF+ ADC/ DAC VREF- Analog: RCs, PLL, ... VSSA ai14125d Caution: In Figure 8, the 4.
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STM32F105xx, STM32F107xx 5.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6.
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Electrical characteristics STM32F105xx, STM32F107xx Table 8. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Value Unit –65 to +150 °C 150 °C Maximum junction temperature 5.3 Operating conditions 5.3.1 General operating conditions Table 9.
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STM32F105xx, STM32F107xx 5.3.2 Electrical characteristics Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 10. Operating conditions at power-up / power-down Symbol Parameter VDD rise time rate tVDD 5.3.
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Electrical characteristics 5.3.4 STM32F105xx, STM32F107xx Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12. Embedded internal reference voltage Symbol VREFINT Parameter Internal reference voltage Conditions Min Typ Max Unit –40 °C < TA < +105 °C 1.16 1.20 1.26 V –40 °C < TA < +85 °C 1.16 1.20 1.
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STM32F105xx, STM32F107xx Electrical characteristics Table 13. Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions fHCLK TA = 105 °C 72 MHz 68 68.4 48 MHz 49 49.2 36 MHz 38.7 38.9 24 MHz 27.3 27.9 16 MHz 20.2 20.5 8 MHz 10.2 10.8 72 MHz 32.7 32.9 48 MHz 25 25.2 External clock(2), all 36 MHz peripherals disabled 24 MHz 20.3 20.6 14.8 15.1 16 MHz 11.2 11.7 8 MHz 6.6 7.
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Electrical characteristics STM32F105xx, STM32F107xx Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled Supply current in Sleep mode IDD External clock(2), all peripherals disabled fHCLK Unit TA = 85 °C TA = 105 °C 72 MHz 48.4 49 48 MHz 33.9 34.4 36 MHz 26.7 27.2 24 MHz 19.3 19.8 16 MHz 14.2 14.8 8 MHz 8.7 9.1 72 MHz 10.1 10.6 48 MHz 8.3 8.75 36 MHz 7.
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STM32F105xx, STM32F107xx Electrical characteristics Figure 10. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values Consumption (µA) 2.5 1.8 V 2V 2.4 V 3.3 V 3.6 V 2 1.5 1 0.5 0 –40 °C 25 °C 70 °C 85 °C 105 °C Temperature (°C) ai17329 Figure 11. Typical current consumption in Stop mode with regulator in Run mode versus temperature at different VDD values 900.00 800.00 Consumption (µA) 700.00 600.00 500.00 3.6 V 400.00 3.3 V 300.00 3V 200.00 2.7 V 2.
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Electrical characteristics STM32F105xx, STM32F107xx Figure 12. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at different VDD values 900.00 Consumption (µA) 800.00 700.00 600.00 500.00 3.6 V 400.00 3.3 V 300.00 3V 200.00 2.7 V 2.4 V 100.00 0.00 –40 °C 25 °C 85 °C 105 °C Temperature (°C) ai17123 Figure 13. Typical current consumption in Standby mode versus temperature at different VDD values 4.50 4.00 Consumption (µA) 3.50 3.00 2.50 3.6 V 2.
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STM32F105xx, STM32F107xx Electrical characteristics Table 17. Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Symbol Parameter Conditions External IDD clock(3) Supply current in Run mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK All peripherals All peripherals disabled enabled(2) 72 MHz 47.3 28.3 48 MHz 32 19.6 36 MHz 24.6 15.4 24 MHz 16.8 10.6 16 MHz 11.8 7.4 8 MHz 5.9 3.7 4 MHz 3.
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Electrical characteristics STM32F105xx, STM32F107xx Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions All peripherals All peripherals enabled(2) disabled 72 MHz 28.2 6 48 MHz 19 4.2 36 MHz 14.7 3.4 24 MHz 10.1 2.5 16 MHz 6.7 2 8 MHz 3.2 1.3 4 MHz 2.3 1.2 2 MHz 1.7 1.16 1 MHz 1.5 1.1 500 kHz 1.3 1.05 125 kHz 1.2 1.05 36 MHz 13.7 2.6 24 MHz 9.3 1.
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STM32F105xx, STM32F107xx Electrical characteristics Table 19. Peripheral current consumption(1) Peripheral Typical consumption at 25 °C ETH_MAC 5.2 OTG_FS 7.7 TIM2 1.5 TIM3 1.5 TIM4 1.5 TIM5 1.5 TIM6 0.6 TIM7 0.3 SPI2 0.2 USART2 0.5 USART3 0.5 UART4 0.5 UART5 0.5 I2C1 0.5 I2C2 0.5 CAN1 0.8 CAN2 0.8 DAC 0.4 GPIO A 0.5 GPIO B 0.5 GPIO C 0.5 GPIO D 0.5 GPIO E 0.5 (2) ADC1 2.1 ADC2(2) 2.0 TIM1 1.7 SPI1 0.4 USART1 0.9 Unit AHB mA APB1 APB2 mA 1.
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Electrical characteristics 5.3.6 STM32F105xx, STM32F107xx External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 20.
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STM32F105xx, STM32F107xx Electrical characteristics Figure 14. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) t tW(HSE) THSE External clock source fHSE_ext OSC _IN IL STM32F10xxx ai14127b Figure 15.
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Electrical characteristics STM32F105xx, STM32F107xx Table 22. HSE 3-25 MHz oscillator characteristics(1) (2) Symbol Conditions Min Oscillator frequency - 3 RF Feedback resistor - - C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 Ω i2 HSE driving current gm Oscillator transconductance fOSC_IN tSU(HSE(4) Parameter Max Unit 25 MHz 200 - kΩ - 30 - pF VDD = 3.
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STM32F105xx, STM32F107xx Electrical characteristics time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 23. LSE oscillator characteristics (fLSE = 32.
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Electrical characteristics STM32F105xx, STM32F107xx Figure 17. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.
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STM32F105xx, STM32F107xx 5.3.7 Electrical characteristics Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. High-speed internal (HSI) RC oscillator Table 24. HSI oscillator characteristics (1) Symbol Parameter Conditions Min Typ Frequency - - 8 DuCy(HSI) Duty cycle - 45 - 55 % - - 1(3) % TA = –40 to 105 °C –2 - 2.5 % TA = –10 to 85 °C –1.
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Electrical characteristics STM32F105xx, STM32F107xx All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 26. Low-power mode wakeup timings Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Parameter Typ Unit Wakeup from Sleep mode 1.8 µs Wakeup from Stop mode (regulator in run mode) 3.6 Wakeup from Stop mode (regulator in low power mode) 5.4 Wakeup from Standby mode 50 µs µs 1.
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STM32F105xx, STM32F107xx 5.3.9 Electrical characteristics Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 29. Flash memory characteristics Symbol tprog tERASE tME IDD Vprog Min(1) Typ Max(1) Unit 16-bit programming time TA = –40 to +105 °C 40 52.5 70 µs Page (1 KB) erase time TA = –40 to +105 °C 20 - 40 ms Mass erase time TA = –40 to +105 °C 20 - 40 ms Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.
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Electrical characteristics STM32F105xx, STM32F107xx Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
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STM32F105xx, STM32F107xx Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 32. EMI characteristics Symbol SEMI 5.3.11 Parameter Peak level Monitored frequency band Conditions VDD = 3.
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Electrical characteristics STM32F105xx, STM32F107xx Table 34. Electrical sensitivities Symbol LU 5.3.12 Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation.
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STM32F105xx, STM32F107xx Electrical characteristics Table 36. I/O static characteristics (continued) Symbol Parameter Standard IO input high level voltage VIH Vhys Ilkg RPU RPD CIO IO FT(1) input high level voltage Conditions Min Typ Max Unit - 0.41*(VDD-2 V)+1.3 V - VDD+0.3 V 0.42*(VDD-2 V)+1 V - VDD > 2 V VDD ≤ 2 V 5.5 V 5.
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Electrical characteristics STM32F105xx, STM32F107xx Figure 18. Standard I/O input characteristics - CMOS port 6)( 6), 6 6 $$ ENT 6 )( #-/3 7)(MIN 7),MAX 6 6 )( $$ QUIREM NDARD RE 6 6), $$ 6 $$ IREMENT 6 ), RD REQU #-/3 STANDA )NPUT RANGE NOT GUARANTEED STA 6$$ 6 AI B Figure 19.
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STM32F105xx, STM32F107xx Electrical characteristics Figure 20. 5 V tolerant I/O input characteristics - CMOS port 6)( 6), 6 6 $$ TS 6 )( UIREMEN ARD REQ 3 STAND #-/ 6 ), 6 $$ T 6 ), 6 $$ REQUIRMEN /3 STANDARD #- 6 )( 6 $$ )NPUT RANGE NOT GUARANTEED 6$$ 6 6$$ AI B Figure 21.
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Electrical characteristics STM32F105xx, STM32F107xx Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/-20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.
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STM32F105xx, STM32F107xx Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 22 and Table 38, respectively. Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 38.
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Electrical characteristics STM32F105xx, STM32F107xx Figure 22. I/O AC characteristics definition 10% 90% 50% 50% 90% 10% EXTERNAL tr(I O)out OUTPUT ON 50 pF tf(I O)out T Maximum frequency is achieved if (t r + t f ) < (2/3)T and if the duty cycle is (45-55%) when loaded by 50 pF ai14131 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 36).
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STM32F105xx, STM32F107xx Electrical characteristics Figure 23. Recommended NRST pin protection VDD External reset circuit(1) RPU NRST(2) Internal Reset Filter 0.1 µF STM32F10xxx ai14132d 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 39. Otherwise the reset will not be taken into account by the device. 5.3.
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Electrical characteristics 5.3.16 STM32F105xx, STM32F107xx Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 9.
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STM32F105xx, STM32F107xx Electrical characteristics Figure 24. I2C bus AC waveforms and measurement circuit VDD 4 .7 kΩ VDD 4 .7 kΩ 100 Ω 100 Ω I²C bus STM32F10x SDA SCL Start repeated Start Start tsu(STA) SDA tf(SDA) tr(SDA) th(STA) tsu(SDA) tw(SCLL) th(SDA) tsu(STO:STA) Stop SCL tw(SCLH) tr(SCL) tf(SCL) tsu(STO) ai14133d 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 42. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.
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Electrical characteristics STM32F105xx, STM32F107xx I2S - SPI interface characteristics Unless otherwise specified, the parameters given in Table 43 for SPI or in Table 44 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
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STM32F105xx, STM32F107xx Electrical characteristics Figure 25. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 26.
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Electrical characteristics STM32F105xx, STM32F107xx Figure 27. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTPUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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STM32F105xx, STM32F107xx Electrical characteristics Table 44.
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Electrical characteristics STM32F105xx, STM32F107xx Figure 28. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2.
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STM32F105xx, STM32F107xx Electrical characteristics USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Speed). Table 45. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 µs 1. Guaranteed by design, not tested in production. Table 46. USB OTG FS DC electrical characteristics Symbol Conditions USB OTG FS operating voltage Min.(1) Typ. Max.(1) Unit - 3.0(2) - 3.
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Electrical characteristics STM32F105xx, STM32F107xx Table 47. USB OTG FS electrical characteristics(1) Driver characteristics Symbol Parameter Conditions Min Max Unit tr Rise time(2) CL = 50 pF 4 20 ns tf Fall time(2) CL = 50 pF 4 20 ns tr/tf 90 110 % - 1.3 2.0 V trfm Rise/ fall time matching VCRS Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal.
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STM32F105xx, STM32F107xx Electrical characteristics Figure 32. Ethernet RMII timing diagram RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667 Table 50.
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Electrical characteristics STM32F105xx, STM32F107xx Table 51.
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STM32F105xx, STM32F107xx Electrical characteristics Table 52. ADC characteristics (continued) Symbol Parameter tlat(2) Injection trigger conversion latency tlatr(2) Regular trigger conversion latency tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) Conditions Min Typ Max Unit fADC = 14 MHz - - 0.214 µs 1/fADC - - - 3(4) fADC = 14 MHz - - 0.143 µs - - - 2(4) 1/fADC fADC = 14 MHz 0.107 - 17.1 µs - 1.5 - 239.
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Electrical characteristics STM32F105xx, STM32F107xx Table 54. ADC accuracy - limited test conditions(1) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(2) fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 3 V to 3.6 V TA = 25 °C Measurements made after ADC calibration ±1.3 ±2 ±1 ±1.5 ±0.5 ±1.5 ±0.7 ±1 ±0.8 ±1.5 Typ Max(3) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.
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STM32F105xx, STM32F107xx Electrical characteristics Figure 34. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4093 (2) ET 7 (1) 6 5 4 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one.
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Electrical characteristics STM32F105xx, STM32F107xx General PCB design guidelines Power supply decoupling should be performed as shown in Figure 36 or Figure 37, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 36.
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STM32F105xx, STM32F107xx 5.3.18 Electrical characteristics DAC electrical specifications Table 56. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage 2.4 - 3.6 V - VREF+ Reference supply voltage 2.4 - 3.
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Electrical characteristics STM32F105xx, STM32F107xx Table 56. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Offset(2) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - ±10 mV Given for the DAC in 12-bit configuration - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain error - - ±0.
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STM32F105xx, STM32F107xx 5.3.19 Electrical characteristics Temperature sensor characteristics Table 57. TS characteristics Symbol TL(1) Parameter Min Typ Max Unit - ±1 ±2 °C 4.0 4.3 4.6 mV/°C 1.34 1.43 1.52 V Startup time 4 - 10 µs ADC sampling time when reading the temperature - - 17.1 µs VSENSE linearity with temperature Avg_Slope(1) Average slope V25(1) tSTART(2) TS_temp(3)(2) Voltage at 25 °C 1. Based on characterization, not tested in production. 2.
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Package characteristics STM32F105xx, STM32F107xx 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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STM32F105xx, STM32F107xx Package characteristics Figure 39. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline Table 58. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A - - 1.700 - - 0.0026 A1 0.270 - - 0.0004 - - A2 - 1.085 - - 0.0017 - A3 - 0.30 - - 0.0005 - A4 - - 0.80 - - 0.0012 b 0.45 0.50 0.55 0.0007 0.0008 0.0009 D 9.85 10.00 10.15 0.
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Package characteristics STM32F105xx, STM32F107xx Figure 40. Recommended PCB design rules (0.80/0.
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STM32F105xx, STM32F107xx Package characteristics Figure 41. LQFP100, 100-pin low-profile quad flat package outline(1) Figure 42. Recommended footprint(1)(2) 0.25 mm 0.10 inch GAGE PLANE k 75 51 D L D1 76 50 0.5 L1 D3 51 75 C 0.3 76 50 16.7 14.3 b E3 E1 E 100 26 1.2 1 100 26 Pin 1 1 identification 25 12.3 25 ccc C 16.7 e A1 ai14906 A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 59.
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Package characteristics STM32F105xx, STM32F107xx Figure 44. Recommended footprint(1)(2) Figure 43. LQFP64 – 64 pin low-profile quad flat package outline(1) A 48 33 A2 0.3 A1 E 49 b E1 12.7 32 0.5 10.3 10.3 e 64 17 1.2 1 D1 c 7.8 L1 D 16 12.7 L ai14909 ai14398b 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 60. LQFP64 – 64 pin low-profile quad flat package mechanical data inches(1) mm Dim. Min Typ Max Min Typ Max A - - 1.60 - - 0.0630 A1 0.
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STM32F105xx, STM32F107xx 6.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 36.
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Package characteristics 6.2.2 STM32F105xx, STM32F107xx Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 62: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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STM32F105xx, STM32F107xx Package characteristics Using the values obtained in Table 61 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 62: Ordering information scheme). Figure 45. LQFP100 PD max vs.
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Part numbering 7 STM32F105xx, STM32F107xx Part numbering Table 62.
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STM32F105xx, STM32F107xx Appendix A A.1 Application block diagrams Application block diagrams USB OTG FS interface solutions Figure 46. USB OTG FS device mode STM32F105xx/STM32F107xx OTG PHY USB OTG Full-speed core DM HNP V BUS VSS ID USB Micro-B connector DP USB Full-speed transceiver To host DP DM VBUS VSS SRP VDD 5 V to VDD Regulator(1) ai15653b 1. Use a regulator if you want to build a bus-powered device.
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Application block diagrams STM32F105xx, STM32F107xx Figure 47. Host connection STM32F105xx/STM32F107xx OTG PHY USB OTG Full-speed core DM HNP V BUS VSS ID USB Std-A connector DP USB full-speed/ low-speed transceiver VDD(2) SRP GPIO GPIO + IRQ Current-limited power distribution 5 V switch OVRCR STMPS2141STR(1) flag EN ai15654b 1. STMPS2141STR needed only if the application has to support bus-powered devices.
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STM32F105xx, STM32F107xx Application block diagrams Figure 48. OTG connection (any protocol) STM32F105xx/STM32F107xx OTG PHY DM ID USB OTG Full-speed core HNP V BUS VSS ID USB Micro-AB connector DP USB full-speed/ low-speed transceiver VDD SRP GPIO GPIO + IRQ Current-limited power distribution 5 V switch OVRCR STMPS2141STR(1) flag EN ai15655b 1. STMPS2141STR needed only if the application has to support bus-powered devices. A.2 Ethernet interface solutions Figure 49.
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Application block diagrams STM32F105xx, STM32F107xx Figure 50. RMII with a 50 MHz oscillator Ethernet PHY 10/100 STM32F107xx MCU Ethernet MAC 10/100 RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] HCLK(1) RMII_CRX_DV RMII = 7 pins RMII + MDC = 9 pins RMII_REF_CLK IEEE1588 PTP Timer input trigger Timestamp TIM2 comparator MDIO MDC /2 or /20 2.5 or 25 MHz synchronous 50 MHz OSC 50 MHz PLL HCLK PHY_CLK 50 MHz XT1 50 MHz ai15657 1. HCLK must be greater than 25 MHz. Figure 51.
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STM32F105xx, STM32F107xx Application block diagrams Figure 52. RMII with a 25 MHz crystal STM32F107xx MCU RMII_TX_EN Ethernet MAC 10/100 RMII_TXD[1:0] RMII_RXD[1:0] HCLK RMII_CRX_DV IEEE1588 PTP 50 MHz Timer input trigger Time stamp TIM2 comparator XTAL 25 MHz Ethernet PHY 10/100 RMII_REF_CLK RMII = 7 pins 50 MHz MDIO RMII + MDC = 9 pins MDC 50 MHz OSC PLLS XT1/XT2 NS DP83848(1) ai15659b 1. The NS DP83848 is recommended as the input jitter requirement of this PHY.
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Application block diagrams A.3 STM32F105xx, STM32F107xx Complete audio player solutions Two solutions are offered, illustrated in Figure 53 and Figure 54. Figure 53 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I2S accuracy on the master clock (0.5% error maximum, see the Serial peripheral interface section in the reference manual for details). Figure 53.
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STM32F105xx, STM32F107xx USB OTG FS interface + Ethernet/I2S interface solutions With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the Ethernet (MII/RMII) interfaces. Figure 55 illustrate the solution. Figure 55.
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Application block diagrams STM32F105xx, STM32F107xx Table 63.
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STM32F105xx, STM32F107xx Application block diagrams Table 64. Applicative current consumption in Run mode, code with data processing running from Flash Symbol IDD parameter Conditions(1) Typ(2) Max(2) 85 °C 105 °C External clock, all peripherals enabled except ethernet, HSE = 8 MHz, fHCLK = 72 MHz, no MCO 57 63 64 External clock, all peripherals enabled except ethernet, HSE = 14.74 MHz, fHCLK = 72 MHz, no MCO 60.
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Revision history STM32F105xx, STM32F107xx Revision history Table 65. Document revision history Date Revision 18-Dec-2008 1 Initial release. 2 I/O information clarified on page 1. Figure 4: STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view corrected. Section 2.3.8: Boot modes updated. PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column, plus small additional changes in Table 5: Pin definitions. Consumption values modified in Section 5.3.
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STM32F105xx, STM32F107xx Revision history Table 65. Document revision history (continued) Date 19-Jun-2009 Revision Changes 3 Section 2.3.8: Boot modes and Section 2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support updated. Section 2.3.24: Remap capability added. Figure 1: STM32F105xx and STM32F107xx connectivity line block diagram and Figure 5: Memory map updated.
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Revision history STM32F105xx, STM32F107xx Table 65. Document revision history (continued) Date 14-Sep-2009 102/104 Revision Changes 4 Document status promoted from Preliminary data to full datasheet. Number of DACs corrected in Table 3: STM32F105xx and STM32F107xx family versus STM32F103xx family. Note 5 added in Table 5: Pin definitions. VRERINT and TCoeff added to Table 12: Embedded internal reference voltage.
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STM32F105xx, STM32F107xx Revision history Table 65. Document revision history (continued) Date 11-May-2010 01-Aug-2011 06-Mar-2014 Revision Changes 5 Added BGA package. Table 5: Pin definitions: ETH_RMII_RXD0 and ETH_RMII_RXD1 added in remap column for PD9 and PD10, respectively.
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STM32F105xx, STM32F107xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.