User manual

page 56
Analog System Lab Kit PRO
experiment 10
The goal of this experiment is to design a Low Dropout regulator using
general purpose OP-Amp and PMOS and study its characteristics with
extension to study characteristics of TPS7250 IC. We aim to design a
linear voltage regulator with high eciency which is used in low noise high
eciency applications.
LDOisusedtoproduceregulatedvoltageforhigheciencylownoiseapplications.
Please view the recorded lectures at [23] for a detailed description of voltage
regulators. In case of DC-DC converter switching takes place (as shown by PWM
waveform) and switching is a source of noise but in LDO no switching takes place
henceitisusedasvoltageregulatorinlownoisehighecientsystems.Asshown
in the circuit below LDO uses PMOS along with OP-Amp so that power dissipation in
OP-Ampisminimalandeciencyishigh.Theregulatedoutputvoltageisgivenby
VV RR
dV V
V
dI
dV
1
021
00
0
0
0
ref
=+
_i
.
Output Characteristics - Measure the load regulation of the system. Load regulation
is given by
VV RR
dV V
V
dI
dV
1
021
00
0
0
0
ref
=+
_i
when Io is varying from minimum to maximum value.
Transfer Characteristics - Measure the line regulation of the system. Line regulation
is given by
VV RR
dV V
V
dI
dV
1
021
00
0
0
0
ref
=+
_i
when
VV RR
dV V
V
dI
dV
1
021
00
0
0
0
ref
=+
_i
is varying from minimum to maximum value.
Measure the ripple rejection by applying the ripple input voltage and measuring
the output ripple voltage.
Measure the output impedance of the LDO, which is given by
VV RR
dV V
V
dI
dV
1
021
00
0
0
0
ref
=+
_i
. We have shown
the sample output of load regulation and line regulation in Figure 10.2.
Generate 3V output when input voltage is varying from 4V to 5V.
10.1 Brief theory and motivation
10.3 Measurements to be taken
10.2Specications
Goal of the experiment
Figure 10.1: Low Dropout Regulator (LDO)
Table 10.1: Variation of Load Regulation with Load Current in an LDO
Figure 10.2: A regulator circuit and its simulated
outputs - line regulation and load regulation
R2
R1 RL
R
+
Vref
VUN
VO
R1
R2
= Vref [1+ ]
1
2
3
4
R5 2k
R 10k
R4 10k
R6 10k
Z1
D1
R3 10k
R2 10k
VF1
V1
+
S.No. Reference Voltage Output Voltage
1
2
3
4