User manual

page 44
Analog System Lab Kit PRO
experiment 7
The goal of this experiment is to make you aware of the functionality of
the Phase Lock Loop commonly referred to as PLL which is primarily used
for a frequency synthesizer in high frequency stable clock generators. From
a crystal of some kHz range, it is possible to generate waveform of GHz
frequency range using a PLL.
Intheloopofself-tunedlterstudiedinexperimentnumber5ifwereplacethe
Voltage Control Filter (VCF) with Voltage Control Oscillator (VCO) (discussed in
experiment6)thenitbecomesPLLasshowninFigure7.1.Thereaderwillbenet
from viewing the recorded lecture at [22].
The sensitivity of the PLL is given by
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
and is equal to
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
, where
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
,
frequency of oscillation of VCO. Hence
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
, which is nothing but
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
Design a PLL to get locked to frequency of 1 kHz.
7.1 Brief theory and motivation
7.2Specications
Goal of the experiment
K
dV
d
VRC
V
dV
d
VRC
V
V
K V
V
V
V
V
K AK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCO c
Q
CQ
i
ref
pd VCO
$
$
# # #
~
~
r
=
=
=
~
~
~
~
VCO
R
C
Vref=0
VI
VO
Vc Control Voltage
Input Frequency
W(Input)
(Output)
(7.1)
Figure 7.1: Phase Locked Loop (PLL) and its characteristics
Figure 7.2: Sample output waveform for the Phase Locked Loop (PLL) Experiment
When no input voltage is applied to the system, the system oscillates at the free
running frequency of the VCO, given by
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
with corresponding control voltage of
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
. If the input is applied to the system with the same frequency as
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
, the PLL
willcontinuetorunatthefreerunningfrequencyandthephasedierencebetween
the two signals
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
and
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
as90˚since
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
is 0 (already explained in Experiment 5
of Chapter 6). As the frequency of input signal is changed, the control voltage will
change correspondingly, so as to lock the output frequency to the input frequency.
Asaresult,thereisachangeofphasedierencebetweenthetwosignalsaway
from90˚.Therangeofinputfrequenciesforwhichoutputfrequenciesgetslocked
totheinputiscalledthelockrangeofthesystem.Thelockrangeis denedas
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
on either side of
K
dV
d
VRC
V
dV
d
VRC
V
V
KV
V
V
V
V
KAK
4
2
0
0
0
VCO
c
r
c
c
r
c
c
VCOc
Q
CQ
i
ref
pd VCO
$
$
###
~
~
r
=
=
=
~
~
~
~
.
-
-
+
+
VG1
+
V2
R1
R4
U3
U4
R5
C1
R2
R3
V1
+
+
VF1
VF3
VF2
10.00
5.00
0.00
-5.00
-10.00
0.00
10.00m
20.00m
30.00m
Time (s)
Output
U2
U1
C2
U 1
C 1
R 1
V G1
U 2
U 3
R 2
R 3
R 5
U 4
R 4
C 2
V F3
+
V F2
V F1
V 1
+
V 2
+