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MFRC631 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.3 — 4 February 2014
227433 95 of 120
NXP Semiconductors
MFRC631
High performance ISO/IEC 14443 A/B reader solution
9.14 Low-power card detection configuration registers
The LPCD registers contain the settings for the low-power card detection. The setting for
LPCD_IMax (6 bits) is done by the two highest bits (bit 7, bit 6) of the registers
LPCD_QMin, LPCD_QMax and LPCD_IMin each.
9.14.1 LPCD_QMin
9.14.2 LPCD_QMax
5RFU
6RFU
7RFU
88
99
10 10
... ...
253 253
254 254
Table 170. Setting for the output divider ratio PLLDiv_Out [7:0]
Value Division
Table 171. LPCD_QMin register (address 3Fh)
Bit 7 6 5 4 3 2 1 0
Symbol LPCD_IMax.5 LPCD_IMax.4 LPCD_QMin
Access
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Table 172. LPCD_QMin bits
Bit Symbol Description
7, 6 LPCD_IMax Defines the highest two bits of the higher border for the LPCD. If the
measurement value of the I channel is higher than LPCD_IMax, a
LPCD interrupt request is indicated by bit IRQ0.LPCDIrq.
5 to 0 LPCD_QMin Defines the lower border for the LPCD. If the measurement value of
the Q channel is higher than LPCD_QMin, a LPCDinterrupt request is
indicated by bit IRQ0.LPCDIrq.
Table 173. LPCD_QMax register (address 40h)
Bit 7 6 5 4 3 2 1 0
Symbol LPCD_IMax.3 LPCD_IMax.2 LPCD_QMax
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