Product data

MFRC631 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.3 — 4 February 2014
227433 94 of 120
NXP Semiconductors
MFRC631
High performance ISO/IEC 14443 A/B reader solution
9.13.4 PLLDiv_Out
Table 166. PLL_Ctrl register bits
Bit Symbol Description
7 to 4 CLkOutSel
• 0h - pin CLKOUT is used as I/O
• 1h - pin CLKOUT shows the output of the analog PLL
• 2h - pin CLKOUT is hold on 0
• 3h - pin CLKOUT is hold on 1
• 4h - pin CLKOUT shows 27.12 MHz from the crystal
• 5h - pin CLKOUT shows 13.56 MHz derived from the crystal
• 6h - pin CLKOUT shows 6.78 MHz derived from the crystal
• 7h - pin CLKOUT shows 3.39 MHz derived from the crystal
• 8h - pin CLKOUT is toggled by the Timer0 overflow
• 9h - pin CLKOUT is toggled by the Timer1 overflow
• Ah - pin CLKOUT is toggled by the Timer2 overflow
• Bh - pin CLKOUT is toggled by the Timer3 overflow
• Ch...Fh - RFU
3 ClkOut_En Enables the clock at Pin CLKOUT
2 PLL_PD PLL power down
1-0 PLLDiv_FB PLL feedback divider (see table 174)
Table 167. Setting of feedback divider PLLDiv_FB [1:0]
Bit 1 Bit 0 Division
0 0 23 (VCO frequency 312Mhz)
0 1 27 (VCO frequency 366MHz)
1 0 28 (VCO frequency 380Mhz)
1 1 23 (VCO frequency 312Mhz)
Table 168. PLLDiv_Out register (address 3Eh)
Bit 7 6 5 4 3 2 1 0
Symbol PLLDiv_Out
Access
rights
r/w
Table 169. PLLDiv_Out bits
Bit Symbol Description
7 to 0 PLLDiv_Out PLL output divider factor; Refer to Section 8.8.2
Table 170. Setting for the output divider ratio PLLDiv_Out [7:0]
Value Division
0RFU
1RFU
2RFU
3RFU
4RFU