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MFRC631 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.3 — 4 February 2014
227433 60 of 120
NXP Semiconductors
MFRC631
High performance ISO/IEC 14443 A/B reader solution
9.4 FIFO configuration register
9.4.1 FIFOControl
FIFOControl defines the characteristics of the FIFO
9.4.2 WaterLevel
Defines the level for FIFO under- and overflow warning levels.This register is extended by
1 bit in FIFOControl in case the 512-byte FIFO mode is activated by setting bit
FIFOControl.FIFOSize.
Table 45. FIFOControl register (address 02h);
Bit 7 6 5 4 3 2 1 0
Symbol FIFOSize HiAlert LoAlert FIFOFlush RFU WaterLevel FIFOLength
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rights
r/w r r w - r/w r
Table 46. FIFOControl bits
Bit Symbol Description
7 FIFOSize Set to logic 1, FIFO size is 255 bytes;
Set to logic 0, FIFO size is 512 bytes.
It is recommended to change the FIFO size only, when the FIFO
content had been cleared.
6 HiAlert Set to logic 1, when the number of bytes stored in the FIFO buffer
fulfils the following equation:
HiAlert = (FIFOSize - FIFOLength) <= WaterLevel
5 LoAlert Set to logic 1, when the number of bytes stored in the FIFO buffer
fulfils the following conditions:
LoAlert =1 if FIFOLength <= WaterLevel
4 FIFOFlush Set to logic 1 empties the FIFO buffer. Reading this bit will always
return 0
3RFU -
2 WaterLevel Defines the bit 8 (MSB) for the waterlevel (extension of WaterLevel).
This bit is only evaluated in the 512-byte FIFO mode. Bits 7..0 are
defined in WaterLevel.
1 to 0 FIFOLength Defines the bit9 (MSB) and bit8 for the FIFO length (extension of
FIFOLength). These two bits are only evaluated in the 512-byte FIFO
mode, The bits 7..0 are defined in FIFOLength.
Table 47. WaterLevel register (address 03h);
Bit 7 6 5 4 3 2 1 0
Symbol WaterLevel
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rights
r/w