Product data

Product data sheet

COMPANY PUBLIC

Rev. 3.3 — 4 February 2014

227433 15 of 120

NXP Semiconductors

MFRC631

High performance ISO/IEC 14443 A/B reader solution

8.4.2.2 Read data

To read out data from the MFRC631 by using the SPI compatible interface the following

byte order has to be used.

The first byte that is sent defines the mode (LSB bit) and the address.

Remark: The Most Significant Bit (MSB) has to be sent first.

8.4.2.3 Write data

To write data to the MFRC631 using the SPI interface the following byte order has to be

used. It is possible to write more than one byte by sending a single address byte

(see.8.5.2.4).

The first send byte defines both, the mode itself and the address byte.

Remark: The Most Significant Bit (MSB) has to be sent first.

8.4.2.4 Address byte

The address byte has to fulfil the following format:

The LSB bit of the first byte defines the used mode. To read data from the MFRC631 the

LSB bit is set to logic 1. To write data to the MFRC631 the LSB bit has to be cleared. The

bits 6 to 0 define the address byte.

NOTE: When writing the sequence [address byte][data1][data2][data3]..., [data1] is written

to address [address byte], [data2] is written to address [address byte + 1] and [data3] is

written to [address byte + 2].

Exception: This auto increment of the address byte is not performed if data is written to

the FIFO address

8.4.2.5 Timing Specification SPI

The timing condition for SPI interface is as follows:

Table 8. Byte Order for MOSI and MISO

byte 0 byte 1 byte 2 byte 3 to n-1 byte n byte n+1

MOSI address 0 address 1 address 2 …….. address n 00h

MISO X data 0 data 1 …….. data n  1data n

Table 9. Byte Order for MOSI and MISO

byte 0 byte 1 byte 2 3 to n-1 byte n byte n + 1

MOSI address 0 data 0 data 1 …….. data n 1 data n

MISOXXX……..XX

Table 10. Address byte 0 register; address MOSI

7 6 5 4 3 2 1 0

address 6 address 5 address 4 address 3 address 2 address 1 address 0 1 (read)

0 (write)

MSB LSB