Datasheet
Thursday, 17 July 2003 MiniProject: Design Aspects Colin K McCord
EEE512J2 – Electronic Product Design Page 34 Chapter 7: Electronic / Software Design
7.3. Digital Circuitry
Figure 7.3a shows the circuit diagram; it is important to note that this is a first draft (prototype) designed to
test the concept of an ECG monitor, this version is not a valid commercial medial product as it does not
comply with all the relative medial standards, for example RS232 communications is not isolated (A isolated
DC to DC converter could be used for this task) and the design has no noise immunity. Allow this design
could be released as a non-medical version (e.g. sports usage) for less than £100 (A lot less than the
predicted retail cost of £453.60 for a fully complied medial product).
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/TOCKI
Vdd
Vss
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
PIC16F877-20/P
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
Vdd
Vss
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SD0
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPPTHV
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
1
2
3
4
5
6
7
8
9
DB9
20MHz
C6
33pF
C7
33pF
ECG
VCC
VCC
16
2
6
14
7
13
89
12
10
11
5
4
3
1
15
VCC
C1+
C1-
V+
C2+
C2-
V-
+5V to +10V
Voltage
Doubler
+10V to -10V
Voltage
Inverter
GND
C4
1uF
C3
1uF
C1
1uF
C2
1uF
C5
1uF
MAX232CPE
VCC
VCC
1
2
3
4
5
6
7
8
9
10
AGND
VA OUT
VREF OUT
VREF IN (A)
DGND
DAC A/DAB B
DB0 (MSB)
DB1
DB2
DB3
20
19
18
17
16
15
14
13
12
11
VB OUT
VREF TRIM
VREF IN (B)
VCC
ENABLE
WRITE
DB7 (LSB)
DB6
DB5
DB4
ZN508E-8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
VCC
WE
CS2
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
M6264P-15
D7
D6
D5
D4
D3
D2
D1
D0
D[7..0]
D2
D1
D0
D3
D4
D5
D6
D7
D4
D5
D6
D7
D3
D2
D1
D0
VCC
A[7..0]
A0
A1 A2
A3
A4
A5
A6
A7
A7
A6
A5
A4
A3
A2
A1
A0
XY
DIP SW
R2
1k
R3
1k
R4
1k
VCC
VCC
C3
C2
C1
C0
C0C1
C2
C3
VCC
R1
1.5k
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
R5
1k
R6
10k
T1
BS170
VCC
Buzzer
d
e
c
g
b
a
f
afbcdeVcc g
VCC
330R
2D
74LS377
1C2
G1
d
e
c
g
b
a
f
afbcdeVcc g
VCC
330R
2D
74LS377
1C2
G1
d
e
c
g
b
a
f
afbcdeVcc g
VCC
330R
2D
74LS377
1C2
G1
C4
C5
C6
C4
C5
C6
C7
C8
C7 C8
Push
Button
R7
1k
VCC
Figure 7.3a. Digital circuit diagram