Datasheet

Thursday, 17 July 2003 MiniProject: Design Aspects Colin K McCord
EEE512J2 – Electronic Product Design Page 8 Chapter 2: Fundamentals
“All the elements of the von Neumann computer are wired together with the one common data highway or
bus. With the CPU acting as the master controller, all information flow is back and forward along these
shared wires. Although this is efficient, it does mean that only one thing can happen at any time. This
phenomenon is sometimes known as the von Neumann bottleneck.” [B3]
Memory
(Program
& Data)
CPU
8-Bit
Figure 2.7a. Simplified illustration of the von Neumann architecture
PICs use the Harvard architecture. The Harvard architecture (Figure 2.7b) is an adaptation of the standard
von Neumann structure with separate program and data memory: data memory is made up by a small
number of 8-bit registers and program memory is 12 to 16-bits wide EPROM, FLASH or ROM.
Memory
(Data)
CPU
Memory
(Program)
8-Bit 12/14/16 Bit
Figure 2.7b. Simplified illustration of the Harvard architecture
Traditional CISC (Complex Instruction Set Computer) machines (Used in: 80X86, 8051, 6800, 68000, etc…)
have many instructions (usually > 100), many addressing modes and it usually takes more than 1 internal
clock cycle to execute. PIC microcontrollers are RISC (Reduced Instruction Set Computer) machines, which
have 33 (12-bit) to 58 (15-bit) instructions, reduced addressing modes (PICs have only direct and indirect),
each instruction does less, but usually executes in one internal clock.
“The combination of single-word instructions, the simplified instruction decoder implicit with the RISC
paradigm and the Harvard separate program and data buses gives a fast, efficient and cost effective
processor implementation.” [B3]
2.7.1. Summary of the PICs Built-in Peripherals
SPI (Serial Peripheral Interface)
uses 3 wires (data in, data out, clock), Master/Slave (can have multiple
masters), very high speed (1.6 Mbps), and full speed simultaneous send and receive (full duplex).
I
2
C (Inter IC) uses 2 wires (data and clock), Master/Slave. There are lots of cheap I
2
C chips available;
typically < 100kbps.
UART (Universal Asynchronous Receiver/Transmitter)
with baud rates of 300bps to 115kbps, 8 or 9 bits,
parity, start and stop bits, etc. Outputs 5V hence an RS232 level converter (e.g. MAX232) is required.
Timers
, both 8 and 16 bits, many have prescalers and some have postscalers. In 14 bit cores they generate
interrupts. External pins (clock in/clock out) can be used for counting events.
Ports
have two control registers: TRIS sets whether each pin is an input or an output and PORT sets their
output bit levels. Note: Other peripherals may steal pins, so in this respect peripheral registers control ports
as well. Most pints have 25mA source/sink (LED enabled), but not all pins, it is important to look up the
datasheet. Floating input pints must be tied off (or set to outputs).
ADCs (Analogue to Digital Converter)
are currently slow, less than 54 KHz sampling rate (8, 10 or 12 bits),
theoretically higher accuracy when PIC is in sleep mode (less digital noise) once the sample is complete the
ADC sends an interrupt waking the PIC. Note that the PIC must wait until the sampling capacitor is charged;
see datasheets.